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Two benefits: 1) We don't accumulate errors from the delay between the timer reset and the deadline preceding it 2) In the future, we may use WAIT to wait for timer expiration, which should cause less bus activity and is should also reduce jitter - regs4740.h (TFR. TFSR, TFCR, TDHR): added more timer registers - ubb-vga.c (until): renamed to "delay" and changed to measure relative to the last deadline - ubb-vga.c (line, hdelay, frame): replaced "until" with "delay" - ubb-vga.c (hdelay, frame, session): reset the timer only once, at the beginning of the session - ubb-vga.c (frame): we didn't wait for the horizontal back porch of the last image line |
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| .. | ||
| ccube.c | ||
| grabfb.c | ||
| Makefile | ||
| mapping.fig | ||
| physmem.c | ||
| ppm.c | ||
| ppm.h | ||
| ppmimg.c | ||
| README | ||
| regs4740.h | ||
| tstimg.c | ||
| ubb-vga-old.c | ||
| ubb-vga.c | ||
| ubb-vga.h | ||
| ubb-vga.pro | ||
| ubb-vga.sch | ||
UBB-VGA - VGA-like output via UBB ================================= Sources ------- Timing and the idea for the voltage divider is from: http://faculty.lasierra.edu/~ehwang/public/mypublications/VGA Monitor Controller.pdf More timing parameters: http://tinyvga.com/vga-timing/640x480@60Hz Signal 8:10 VGA ------- ------- --- R DAT2 1 VSYNC DAT3 14 HSYNC CMD 13 G DAT0 2 B DAT1 3 GND GND 5 http://en.wikipedia.org/wiki/VGA_connector Timing ------ Since the Ingenic CPUs take about 8.5 PCLK cycles for a GPIO set or clear, and we can only set or clear a set of signals in GPIO operation, but not set some and clear others, we cannot have a real 320 horizontal pixels. Instead, set and clear operations alternate. This means that the best-case resolution is equivalent to 320 pixels (if the original pixel boundaries coincide with the set/clear phases), but it can be as low as 160 pixels if the boundaries don't match. Furthermore, timing is still a bit too tight. We therefore use a pixel clock that's about 10% slower than the original. Luckily, most monitors don't mind. Single/double mode ------------------ In single mode, only one set/clear can be performed per pixel. They are arranges such that the first pixel can only turn on channels, the following pixel can only turn off channels, and so on. In double mode, a set and a clear is performed per pixel. This changes the timing such that it differs substantially from VGA, but some monitors can still synchronize with this. The resulting signals for various bit patterns are shown in mapping.fig Each group shows the input pixels, and signal for single mode, and the signal for double mode. "S" indicates a point where the channel can be turned on, "C" indicates a point where it can be turned off. Note that there are probably other mapping algorithms that would yield better results. The mapping is not a very performance-critical part of ubb-vga. Improvements are welcome. Compatibility ------------- ubb-vga in single mode has been tested with the following monitors: Display Monitor size Quality ----------------------- --------------- ---------------------------------- Xenon XEN-1510T 15", 1024x768 good Samsung 206NW 20", 1680x1050 poor (horizontal instability) LG W2243C 22", 1920x1080 acceptable (slight instability) LG W2243L 22", 1920x1080 acceptable (slight instability) In double mode: Display Pixels missing Quality left/right ----------------------- --------------- ------------------ Xenon XEN-1510T 5 / 25 good To do ----- - use timer half interrupt and WAIT to synchronize (less bus traffic and hopefully better granularity) - recover from DMA lockup - use color cube map (5x5x5 bits) - read/write raw frame buffer - consider prefetching first word of each line, to make DRAM controller open the row and reduce DMA startup latency