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The history of the split prefetch code: Once up on a time, I thought that it was important to stay very close to the "official" pixel clock. We could do this when copying 32 bit words from cache to the GPIO set/clear registers, but not when shifting 8 bit values as we do now. One problem with 32 bit values is that transferring that amount of data exceeds the time available in the hsync pulse. Hence the idea to split the prefetch between hsync pulse and horizontal front porch. Note that we also split prefetches between the two VGA lines of each QVGA line. This commit does not change that mechanism. - ubb-vga.c (line, frame): removed code fragments for prefetch split between hsync pulse and front porch - ubb-vga.c (line, frame): remove code fragments for measuring time relative to the rising edge of hsync (and letting the prefetch time control the hsync length), not the falling edge |
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Sources ------- Timing and the idea for the voltage divider is from: http://faculty.lasierra.edu/~ehwang/public/mypublications/VGA Monitor Controller.pdf More timing parameters: http://tinyvga.com/vga-timing/640x480@60Hz Signal 8:10 VGA ------- ------- --- R DAT2 1 VSYNC DAT3 14 HSYNC CMD 13 G DAT0 2 B DAT1 3 GND GND 5 http://en.wikipedia.org/wiki/VGA_connector Timing ------ Since the Ingenic CPUs take about 8.5 PCLK cycles for a GPIO set or clear, and we can only set or clear a set of signals in GPIO operation, but not set some and clear others, we cannot have a real 320 horizontal pixels. Instead, set and clear operations alternate. This means that the best-case resolution is equivalent to 320 pixels (if the original pixel boundaries coincide with the set/clear phases), but it can be as low as 160 pixels if the boundaries don't match. Furthermore, timing is still a bit too tight. We therefore use a pixel clock that's about 10% slower than the original. Luckily, most monitors don't mind.