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242 lines
8.2 KiB
C
242 lines
8.2 KiB
C
/*
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* include/ubb/regs4740.h - Jz4740 register definitions (subset)
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*
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* Written 2011-2012 by Werner Almesberger
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* Copyright 2011-2012 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef UBB_REGS4740_H
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#define UBB_REGS4740_H
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#include <stdint.h>
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#include <ubb/regbase.h>
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#define _CGU(n) REG(0x0000000+(n))
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#define _INTC(n) REG(0x0001000+(n))
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#define _TCU(n) REG(0x0002000+(n))
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#define _MSC(n) REG(0x0021000+(n))
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#define _DMAC(n) REG(0x3020000+(n))
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#define _LCD(n) REG(0x3050000+(n))
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#define CPCCR _CGU(0x0000) /* Clock Control */
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#define CLKGR _CGU(0x0020) /* Clock Gate */
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#define MSCCDR _CGU(0x0068) /* MSC device clock divider */
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#define ICMR _INTC(0x04) /* Interrupt controller mask */
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#define ICMSR _INTC(0x08) /* Interrupt controller mask set */
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#define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */
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#define TSSR _TCU(0x2c) /* Timer STOP set */
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#define TSCR _TCU(0x3c) /* Timer STOP clear */
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#define TESR _TCU(0x14) /* Timer counter enable set */
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#define TECR _TCU(0x18) /* Timer counter enable clear */
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#define TFR _TCU(0x20) /* Timer flag */
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#define TFSR _TCU(0x24) /* Timer flag set */
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#define TFCR _TCU(0x28) /* Timer flag clear */
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#define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */
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#define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */
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#define TDHR(n) _TCU(0x44+0x10*(n)) /* Timer data half */
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#define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */
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/* MSC */
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#define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */
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#define MSC_STRPCRL_EXIT_MULTIPLE (1 << 7)
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#define MSC_STRPCRL_EXIT_TRANSFER (1 << 6)
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#define MSC_STRPCRL_START_READWAIT (1 << 5)
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#define MSC_STRPCRL_STOP_READWAIT (1 << 4)
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#define MSC_STRPCRL_RESET (1 << 3)
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#define MSC_STRPCRL_START_OP (1 << 2)
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#define MSC_STRPCRL_START_CLOCK (1 << 1)
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#define MSC_STRPCRL_STOP_CLOCK (1 << 0)
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#define MSC_STAT _MSC(0x04) /* MSC status */
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#define MSC_STAT_IS_RESETTING (1 << 15)
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#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
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#define MSC_STAT_PRG_DONE (1 << 13)
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#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
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#define MSC_STAT_END_CMD_RES (1 << 11)
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#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) /* almost full */
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#define MSC_STAT_IS_READWAIT (1 << 9)
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#define MSC_STAT_CLK_EN (1 << 8)
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#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
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#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
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#define MSC_STAT_CRC_RES_ERR (1 << 5)
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#define MSC_STAT_CRC_READ_ERROR (1 << 4)
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#define MSC_STAT_CRC_WRITE_ERROR_MASK (3 << MSC_STAT_CRC_WRITE_ERROR_SHIFT)
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#define MSC_STAT_CRC_WRITE_ERROR_SHIFT 2
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#define MSC_STAT_CRC_WRITE_ERROR_ERROR 1 /* error reported */
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#define MSC_STAT_CRC_WRITE_ERROR_NOSTAT 2 /* no CRC status */
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#define MSC_STAT_TIME_OUT_RES (1 << 1)
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#define MSC_STAT_TIME_OUT_READ (1 << 0)
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#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */
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#define MSC_CLKRT_MASK 7
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#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */
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#define MSC_CMDAT_IO_ABORT (1 << 11)
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#define MSC_CMDAT_BUS_WIDTH_MASK (3 << MSC_CMDAT_BUS_WIDTH_SHIFT)
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#define MSC_CMDAT_BUS_WIDTH_SHIFT 9
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#define MSC_CMDAT_BUS_WIDTH_1 0
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#define MSC_CMDAT_BUS_WIDTH_4 2
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#define MSC_CMDAT_DMA_EN (1 << 8)
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#define MSC_CMDAT_INIT (1 << 7)
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#define MSC_CMDAT_BUSY (1 << 6)
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#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
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#define MSC_CMDAT_WRITE_READ (1 << 4)
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#define MSC_CMDAT_DATA_EN (1 << 3)
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#define MSC_CMDAT_RESPONSE_FORMAT_MASK (7 << MSC_CMDAT_RESPONSE_FORMAT_SHIFT)
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#define MSC_CMDAT_RESPONSE_FORMAT_SHIFT 0
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#define MSC_CMDAT_RESPONSE_FORMAT_NONE 0
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#define MSC_CMDAT_RESPONSE_FORMAT_R1 1 /* or R1b */
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#define MSC_CMDAT_RESPONSE_FORMAT_R2 2
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#define MSC_CMDAT_RESPONSE_FORMAT_R3 3
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#define MSC_CMDAT_RESPONSE_FORMAT_R4 4
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#define MSC_CMDAT_RESPONSE_FORMAT_R5 5
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#define MSC_CMDAT_RESPONSE_FORMAT_R6 6
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#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */
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#define MSC_RESTO_MASK 0xff /* in MSC_CLK */
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#define MSC_RDTO _MSC(0x14) /* MMC/SD read time out */
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#define MSC_RDTO_MASK 0xffff /* in CLK_SRC/256 */
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#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */
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#define MSC_BLKLEN_MASK 0xfff
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#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */
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#define MSC_NOB_MASK 0xffff
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#define MSC_SNOB _MSC(0x20) /* MMC/SD successful blocks */
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#define MSC_SNOB_MASK 0xffff
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#define MSC_IMASK _MSC(0x24) /* MMC/SD interrupt mask */
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#define MSC_INT_SDIO (1 << 7)
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#define MSC_INT_TXFIFO_WR_REQ (1 << 6)
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#define MSC_INT_RXFIFO_RD_REQ (1 << 5)
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#define MSC_INT_END_CMD_RES (1 << 2)
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#define MSC_INT_PRG_DONE (1 << 1)
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#define MSC_INT_DATA_TRAN_DONE (1 << 0)
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#define MSC_IREG _MSC(0x28) /* MMC/SD interrupt */
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#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */
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#define MSC_CMD_MASK 0x3f
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#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */
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#define MSC_RES _MSC(0x34) /* MMC?SD response FIFO */
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#define MSC_RXFIFO_MASK 0xffff /* 8 x 16 bits */
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#define MSC_RXFIFO _MSC(0x38) /* MMC/SD receive data FIFO */
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#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */
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/* DMA */
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#define _DMAn(n, r) _DMAC(0x20*(n)+(r))
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#define DSA(n) _DMAn(n, 0x00) /* DMA source address */
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#define DTA(n) _DMAn(n, 0x04) /* DMA target address */
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#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */
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#define DTC_MASK 0xffffff
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#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */
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#define DRT_MASK 0x1f
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#define DRT_AUTO 8 /* external to external */
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#define DRT_UART_TX 20
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#define DRT_UART_RX 21
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#define DRT_SSI_TX 22
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#define DRT_SSI_RX 23
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#define DRT_AIC_TX 24
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#define DRT_AIC_RX 25
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#define DRT_MSC_TX 26
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#define DRT_MSC_RX 27
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#define DRT_TCU 28
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#define DRT_SADC 29
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#define DRT_SLCD 30
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#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */
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#define DCS_NDES (1 << 31) /* No-Descriptor Transfer */
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#define DCS_CDOA_MASK (0xff << DCS_CDOA_SHIFT)
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/* Copy of Descriptor Offset Address */
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#define DCS_CDOA_SHIFT 16
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#define DCS_INV (1 << 6) /* Descriptor invalid error */
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#define DCS_AR (1 << 4) /* Address error */
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#define DCS_TT (1 << 3) /* Transfer terminated */
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#define DCS_HLT (1 << 2) /* DMA halt */
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#define DCS_CT (1 << 1) /* Link DMA transfer end */
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#define DCS_CTE (1 << 0) /* Channel enabled */
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#define DCM(n) _DMAn(n, 0x14) /* DMA command */
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#define DCM_SAI (1 << 23) /* Source address increment */
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#define DCM_DAI (1 << 22) /* Destination address increment */
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#define DCM_RDIL_MASK (15 << DCM_RDIL_SHIFT)
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/* Request Detection Interval Length */
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#define DCM_RDIL_SHIFT 16
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#define DCM_RDIL_0 0
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#define DCM_RDIL_2 1 /* 2 units, etc. */
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#define DCM_RDIL_4 2
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#define DCM_RDIL_8 3
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#define DCM_RDIL_12 4
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#define DCM_RDIL_16 5
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#define DCM_RDIL_20 6
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#define DCM_RDIL_24 7
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#define DCM_RDIL_28 8
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#define DCM_RDIL_32 9
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#define DCM_RDIL_48 10
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#define DCM_RDIL_60 11
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#define DCM_RDIL_64 12
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#define DCM_RDIL_124 13
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#define DCM_RDIL_128 14
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#define DCM_RDIL_200 15
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#define DCM_SP_MASK (3 << DCM_SP_SHIFT) /* Source port width */
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#define DCM_SP_SHIFT 14
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#define DCM_SP_32 0 /* 32 bit */
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#define DCM_SP_8 1
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#define DCM_SP_16 2
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#define DCM_DP_MASK (3 << DCM_DP_SHIFT) /* Destination port width */
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#define DCM_DP_SHIFT 12
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#define DCM_DP_32 0 /* 32 bit */
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#define DCM_DP_8 1
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#define DCM_DP_16 2
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#define DCM_TSZ_MASK (7 << DCM_TSZ_SHIFT) /* Transfer data size (unit) */
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#define DCM_TSZ_SHIFT 8
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#define DCM_TSZ_32BIT 0
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#define DCM_TSZ_8BIT 1
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#define DCM_TSZ_16BYTE 3
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#define DCM_TSZ_32BYTE 4
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#define DCM_TM (1 << 7) /* Transfer mode (0 single, 1 block) */
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#define DCM_V (1 << 4) /* Descriptor valid */
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#define DCM_VM (1 << 3) /* Descriptor valid mode */
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#define DCM_VIE (1 << 2) /* DMA valid error Interrupt Enable */
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#define DCM_TIE (1 << 1) /* Transfer Interrupt Enable (TIE) */
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#define DCM_LINK (1 << 0) /* Descriptor link enable */
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#define DMAC _DMAC(0x300) /* DMA control */
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#define DMAC_PM_MASK (3 << DMAC_PM_SHIFT)
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/* Channel priority mode */
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#define DMAC_PM_SHIFT 8
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#define DMAC_PM_012345 0 /* CH0 > CH1 > .. */
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#define DMAC_PM_023145 1
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#define DMAC_PM_201345 2
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#define DMAC_PM_RR 3 /* Round robin */
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#define DMAC_HLT (1 << 3) /* Global halt status */
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#define DMAC_AR (1 << 2) /* Global address error status */
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#define DMAC_DMAE (1 << 0) /* Global DMA transfer enable */
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#define DDR _DMAC(0x308) /* DMA doorbell */
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#define LCDCTRL _LCD(0x30) /* LCD control */
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#endif /* !UBB_REGS4740_H */
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