Version 20100903:

- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
  a bad trace. According to simulations, 22 pF should be more than enough.

- added wire connecting uSD-side ground plane to ground plane at outer edge,
  to improve CLK signal return. (Probably unnecessary, too.)

- the footprint of the transistor (Q1) is reversed :-( It works after
  converting the chip from SOT to PLCC.

- not an erratum, but with experiments showing power-on reset to be
  reliable, we can consider removing the hardware reset circuit. This will
  also simplify the layout.

Version 20100908:

- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
  this.

- work-around on second 20100908 board: replace the resistive divider with
  a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:

  C7 -> 0 R
  R3 -> 33 pF
  R4 -> 220 pF

  Applied work-around also to first 20100908 board after confirming dismal
  performance caused by clock instability.

- considering that the clock input has a Vpp of only 400-500 mV, we should
  have a ground plane also under as much of the the clock circuit as
  possible.

- via between pins 1 and 32 is too close to the chip for DIY PCBs

Version 20100912:

- zone fill did not reach upper GND end of antenna. This was not intended,
  but may be harmless or even an improvement.
