ben-wpan/atusd/ERRATA

- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
  a bad trace. According to simulations, 22 pF should be more than enough.

- added wire connecting uSD-side ground plane to ground plane at outer edge,
  to improve CLK signal return. (Probably unnecessary, too.)

- the footprint of the transistor (Q1) is reversed :-( It works after
  converting the chip from SOT to PLCC.
First part of the board bringup: power and clock. - atusd/ERRATA: variations of the circuit being debugged from the design - tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable the board and (in the future) establish communication - atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative load from scope probe 2010-09-05 05:14:57 +03:00			`- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be`
			`a bad trace. According to simulations, 22 pF should be more than enough.`

			`- added wire connecting uSD-side ground plane to ground plane at outer edge,`
			`to improve CLK signal return. (Probably unnecessary, too.)`
Next part of board bringup: reset and power cycling. - atusd/ERRATA: one more problem: the transistor footprint is wrong - atusd/tools/lib/atusd.c (atusd_cycle, atusd_reset): added power cycling and hardware reset - atusd/tools/lib/atusd.h: be nice and make a header file - atusd/tools/try.c: be nice and use header files (caught a bug as well) 2010-09-05 20:07:01 +03:00
			`- the footprint of the transistor (Q1) is reversed :-( It works after`
			`converting the chip from SOT to PLCC.`