2010-09-05 05:14:57 +03:00
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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2010-09-05 20:07:01 +03:00
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#include <unistd.h>
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2010-09-05 05:14:57 +03:00
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#include <fcntl.h>
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#include <sys/mman.h>
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enum {
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VDD_OFF = 1 << 6, /* VDD disable, PD06 */
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MxSx = 1 << 8, /* CMD, PD08 */
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CLK = 1 << 9, /* CLK, PD09 */
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SCLK = 1 << 10, /* DAT0, PD10 */
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SLP_TR = 1 << 11, /* DAT1, PD11 */
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IRQ = 1 << 12, /* DAT2, PD12 */
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nSEL = 1 << 13, /* DAT3/CD, PD13 */
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};
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#define SOC_BASE 0x10000000
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#define REG(n) (*(volatile uint32_t *) (dsc->mem+(n)))
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#define CGU(n) REG(0x00000+(n))
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#define GPIO(n) REG(0x10000+(n))
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#define MSC(n) REG(0x21000+(n))
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#define PDDATS GPIO(0x314) /* port D data set */
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#define PDDATC GPIO(0x318) /* port D data clear */
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#define PDFUNS GPIO(0x344) /* port D function set */
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#define PDFUNC GPIO(0x348) /* port D function clear */
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#define PDDIRS GPIO(0x364) /* port D direction set */
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#define PDDIRC GPIO(0x368) /* port D direction clear */
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#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */
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#define MSC_CLKRT MSC(0x08) /* MSC Clock Rate */
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#define CLKGR CGU(0x0020) /* Clock Gate */
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#define MSCCDR CGU(0x0068) /* MSC device clock divider */
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#define PAGE_SIZE 4096
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struct atusd_dsc {
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int fd;
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void *mem;
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};
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struct atusd_dsc *atusd_open(void)
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{
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struct atusd_dsc *dsc;
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dsc = malloc(sizeof(*dsc));
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if (!dsc) {
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perror("malloc");
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exit(1);
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}
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dsc->fd = open("/dev/mem", O_RDWR);
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if (dsc->fd < 0) {
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perror("/dev/mem");
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exit(1);
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}
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dsc->mem = mmap(NULL, PAGE_SIZE*3*16, PROT_READ | PROT_WRITE,
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MAP_SHARED, dsc->fd, SOC_BASE);
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if (dsc->mem == MAP_FAILED) {
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perror("mmap");
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exit(1);
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}
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/* set the output levels */
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PDDATS = nSEL | VDD_OFF;
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PDDATC = SCLK | SLP_TR;
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/* take the GPIOs away from the MMC controller */
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PDFUNC = MxSx | SCLK | SLP_TR | IRQ | nSEL;
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PDFUNS = CLK;
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/* set the pin directions */
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PDDIRC = IRQ;
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PDDIRS = MxSx | CLK | SCLK | SLP_TR | nSEL;
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/* enable power */
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PDDATC = VDD_OFF;
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/* set the MSC clock to 316 MHz / 21 = 16 MHz */
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MSCCDR = 20;
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/*
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* Enable the MSC clock. We need to do this before accessing any
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* registers of the MSC block !
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*/
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CLKGR &= ~(1 << 7);
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/* bus clock = MSC clock / 1 */
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MSC_CLKRT = 0;
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/* start MMC clock output */
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MSC_STRPCL = 2;
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return dsc;
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}
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void atusd_close(struct atusd_dsc *dsc)
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{
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2010-09-05 20:07:01 +03:00
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/* stop the MMC bus clock */
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2010-09-05 05:14:57 +03:00
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MSC_STRPCL = 1;
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/* cut the power */
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PDDATS = VDD_OFF;
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/* make all MMC pins inputs */
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PDDIRC = MxSx | CLK | SCLK | SLP_TR | IRQ | nSEL;
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}
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2010-09-05 20:07:01 +03:00
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void atusd_cycle(struct atusd_dsc *dsc)
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{
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/* stop the MMC bus clock */
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MSC_STRPCL = 1;
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/* drive all outputs low (including the MMC bus clock) */
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PDDATC = MxSx | CLK | SCLK | SLP_TR | nSEL;
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/* make the MMC bus clock a regular output */
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PDFUNC = CLK;
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/* cut the power */
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PDDATS = VDD_OFF;
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/* Power drains within about 20 ms. Wait 100 ms to be sure. */
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usleep(100*1000);
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/* drive nSS high */
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PDDATS = nSEL;
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/* supply power */
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PDDATS = VDD_OFF;
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/* return the bus clock output to the MMC controller */
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PDFUNS = CLK;
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/* start MMC clock output */
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MSC_STRPCL = 2;
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}
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void atusd_reset(struct atusd_dsc *dsc)
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{
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/* activate reset */
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PDDATS = SLP_TR;
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PDDATC = nSEL;
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/*
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* Data sheet says 625 ns, programmer's guide says 6 us. Whom do we
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* trust ?
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*/
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usleep(6);
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/* release reset */
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PDDATS = nSEL;
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PDDATC = SLP_TR;
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}
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