2011-06-09 18:48:44 +03:00
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/*
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* fw/board_app.c - Board-specific functions (for the application)
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*
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* Written 2011 by Werner Almesberger
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* Copyright 2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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2011-06-20 21:49:33 +03:00
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#include <stddef.h>
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2011-06-09 18:48:44 +03:00
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#include <stdint.h>
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#include <avr/io.h>
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2011-06-11 07:59:03 +03:00
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#include <avr/interrupt.h>
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2011-06-09 18:48:44 +03:00
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#define F_CPU 8000000UL
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#include <util/delay.h>
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2011-06-20 21:49:33 +03:00
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#include "usb.h"
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#include "at86rf230.h"
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2011-06-09 18:48:44 +03:00
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#include "board.h"
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#include "spi.h"
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2011-06-11 07:59:03 +03:00
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static volatile uint32_t timer_h = 0; /* 2^(16+32) / 8 MHz = ~1.1 years */
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2011-06-09 18:48:44 +03:00
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void reset_cpu(void)
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{
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WDTCSR = 1 << WDE;
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}
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uint8_t read_irq(void)
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{
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return PIN(IRQ_RF);
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}
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void slp_tr(void)
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{
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SET(SLP_TR);
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CLR(SLP_TR);
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}
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2011-06-11 07:59:03 +03:00
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ISR(TIMER1_OVF_vect)
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2011-06-09 18:48:44 +03:00
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{
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timer_h++;
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}
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2011-06-11 17:06:18 +03:00
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uint64_t timer_read(void)
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2011-06-09 18:48:44 +03:00
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{
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uint32_t high;
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uint8_t low, mid;
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do {
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2011-06-11 07:59:03 +03:00
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if (TIFR1 & (1 << TOV1)) {
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TIFR1 = 1 << TOV1;
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timer_h++;
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}
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2011-06-09 18:48:44 +03:00
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high = timer_h;
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low = TCNT1L;
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mid = TCNT1H;
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}
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while (TIFR1 & (1 << TOV1));
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/*
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* We need all these casts because the intermediate results are handled
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* as if they were signed and thus get sign-expanded. Sounds wrong-ish.
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*/
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return (uint64_t) high << 16 | (uint64_t) mid << 8 | (uint64_t) low;
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}
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2011-06-11 07:52:16 +03:00
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void timer_init(void)
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{
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/* configure timer 1 as a free-running CLK counter */
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TCCR1A = 0;
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TCCR1B = 1 << CS10;
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2011-06-11 07:59:03 +03:00
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/* enable timer overflow interrupt */
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TIMSK1 = 1 << TOIE1;
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2011-06-11 07:52:16 +03:00
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}
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2011-06-09 18:48:44 +03:00
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int gpio(uint8_t port, uint8_t data, uint8_t dir, uint8_t mask, uint8_t *res)
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{
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2011-06-21 05:11:09 +03:00
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EIMSK = 0; /* recover INT_RF to ATUSB_GPIO_CLEANUP or an MCU reset */
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2011-06-21 02:50:22 +03:00
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2011-06-09 18:48:44 +03:00
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switch (port) {
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case 1:
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DDRB = (DDRB & ~mask) | dir;
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PORTB = (PORTB & ~mask) | data;
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break;
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case 2:
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DDRC = (DDRC & ~mask) | dir;
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PORTC = (PORTC & ~mask) | data;
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break;
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case 3:
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DDRD = (DDRD & ~mask) | dir;
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PORTD = (PORTD & ~mask) | data;
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break;
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default:
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return 0;
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}
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/* disable the UART so that we can meddle with these pins as well. */
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2011-06-09 20:02:26 +03:00
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spi_off();
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2011-06-09 18:48:44 +03:00
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_delay_ms(1);
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switch (port) {
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case 1:
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res[0] = PINB;
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res[1] = PORTB;
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res[2] = DDRB;
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break;
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case 2:
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res[0] = PINC;
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res[1] = PORTC;
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res[2] = DDRC;
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break;
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case 3:
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res[0] = PIND;
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res[1] = PORTD;
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res[2] = DDRD;
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break;
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}
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return 1;
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}
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2011-06-20 21:49:33 +03:00
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2011-06-21 05:11:09 +03:00
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void gpio_cleanup(void)
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{
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EIMSK = 1 << 0;
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}
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2011-06-23 19:03:34 +03:00
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static void done(void *user)
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2011-06-20 21:49:33 +03:00
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{
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2011-06-23 19:03:34 +03:00
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led(0);
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2011-06-23 15:41:40 +03:00
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}
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atusb/fw/: added improved support for interrupt synchronization
At an interrupt barrier, the host must be able to ensure that no
interrupt generated before reaching the barrier is still pending and
will be delivered after crossing the barrier.
For this, we introduce the following concept:
- interrupts have a serial number. This number is sent to the host
on EP 1 (currently bulk) to signal the interrupt, instead of the
zero byte we used previously.
- the new request ATUSB_SPI_WRITE2_SYNC returns the interrupt
serial number from after the register write (the register write
itself is the interrupt barrier).
- the host can now check if the serial indicated from bulk and the
serial from ATUSB_SPI_WRITE2_SYNC are the same. If yes, interrupts
are synchronized. If not, it has to wait for the interrupt to be
signaled on EP 1.
We should also consider the case that the interrupt serial has gotten
ahead of ATUSB_SPI_WRITE2_SYNC. But that seems to happen rarely. In
any case, it's something for the host driver to worry about, not for
the firmware.
- board.h (irq_serial), board_app.c (irq_serial, INT0_vect): count
the interrupt serial number and return it when signaling the
interrupt
- include/atusb/ep0.h (ATUSB_SPI_WRITE2_SYNC), ep0.c (my_setup):
new request ATUSB_SPI_WRITE2_SYNC that does a register write, then
returns the interrupt serial
2011-07-07 21:51:07 +03:00
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uint8_t irq_serial;
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2011-06-23 15:41:40 +03:00
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ISR(INT0_vect)
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{
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2011-06-23 19:03:34 +03:00
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if (eps[1].state == EP_IDLE) {
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led(1);
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atusb/fw/: added improved support for interrupt synchronization
At an interrupt barrier, the host must be able to ensure that no
interrupt generated before reaching the barrier is still pending and
will be delivered after crossing the barrier.
For this, we introduce the following concept:
- interrupts have a serial number. This number is sent to the host
on EP 1 (currently bulk) to signal the interrupt, instead of the
zero byte we used previously.
- the new request ATUSB_SPI_WRITE2_SYNC returns the interrupt
serial number from after the register write (the register write
itself is the interrupt barrier).
- the host can now check if the serial indicated from bulk and the
serial from ATUSB_SPI_WRITE2_SYNC are the same. If yes, interrupts
are synchronized. If not, it has to wait for the interrupt to be
signaled on EP 1.
We should also consider the case that the interrupt serial has gotten
ahead of ATUSB_SPI_WRITE2_SYNC. But that seems to happen rarely. In
any case, it's something for the host driver to worry about, not for
the firmware.
- board.h (irq_serial), board_app.c (irq_serial, INT0_vect): count
the interrupt serial number and return it when signaling the
interrupt
- include/atusb/ep0.h (ATUSB_SPI_WRITE2_SYNC), ep0.c (my_setup):
new request ATUSB_SPI_WRITE2_SYNC that does a register write, then
returns the interrupt serial
2011-07-07 21:51:07 +03:00
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irq_serial++;
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usb_send(&eps[1], &irq_serial, 1, done, NULL);
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2011-06-23 19:03:34 +03:00
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}
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2011-06-20 21:49:33 +03:00
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}
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void board_app_init(void)
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{
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/* enable INT0, trigger on rising edge */
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EICRA = 1 << ISC01 | 1 << ISC00;
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2011-06-21 02:50:22 +03:00
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EIMSK = 1 << 0;
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2011-06-20 21:49:33 +03:00
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}
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