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38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
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Correct atusd clock voltage divider
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According to section 9.6.3 of the data sheet, an external clock supplied
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to the AT86RF230 has a minimum peak-to-peak voltage of 400 mV and a
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maximum of only 500 mV. Furthermore, the signal must be DC-free.
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The voltage divider in the 20100903 and 20100908 designs is too sensitive
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to interference and the PLL constantly unlocks, rendering the device
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dysfunctional.
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A more robust divider circuit can be obtained with the following
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replacements: C7 -> 0R, R3 -> 33 pF, R4 -> 220 pF. After reworking the
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20100908 boards, they no longer suffer PLL unlocks.
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A Qucs simulation of the circuit can be found in ../atusd/sim/cdiv.sim
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Frequency measurements yield the following results:
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Host Board Error Meas. accuracy
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(f, ppm) (ppm, nom.)
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------- --------------- --------------- ---------------
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Ben #2 20100908-A +2 99.7
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+1 99.6
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Ben #1 20100908-A +23 99.7
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+24 99.9
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Ben #1 20100908-B +24 99.4
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+24 99.7
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Ben #2 20100908-B +2 99.8
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+2 99.9
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The Ben's 12 MHz crystal has a tolerance of +/- 30 ppm, which is better
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than the +/- 40 ppm required by IEEE 802.15.4.
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What remains to be verified is whether this change causes interferences
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that may affect transceiver performance and may also violate emission
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regulations.
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