From 6e726d1fb90ec8f182984a426ea05b15b5adc3b8 Mon Sep 17 00:00:00 2001
From: Werner Almesberger <werner@openmoko.org>
Date: Thu, 9 Sep 2010 12:35:47 -0300
Subject: [PATCH] Improved clock stability by using a capacitative divider and
 found more minor issues.

- atusd/ERRATA: work around the clock instability by replacing the
  resistive divider with a capacitative divider
- atusd/ERRATA: a ground plane under the clock circuit would also be good to
  have
- atusd/ERRATA: via near pin 1 is too close to the chip if we need to cut
  wires (in DIY boards)
- atusd/sim/cdiv.sch: simulation of the capacitative divider
---
 atusd/ERRATA       | 13 +++++++++++++
 atusd/sim/cdiv.sch | 47 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 atusd/sim/cdiv.sch

diff --git a/atusd/ERRATA b/atusd/ERRATA
index 5c7ce42..4004deb 100644
--- a/atusd/ERRATA
+++ b/atusd/ERRATA
@@ -17,3 +17,16 @@ Version 20100908:
 
 - SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
   this.
+
+- work-around on second 20100908 board: replace the resistive divider with
+  a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:
+
+  C7 -> 0 R
+  R3 -> 33 pF
+  R4 -> 220 pF
+
+- considering that the clock input has a Vpp of only 400-500 mV, we should
+  have a ground plane also under as much of the the clock circuit as
+  possible.
+
+- via between pins 1 and 32 is too close to the chip for DIY PCBs
diff --git a/atusd/sim/cdiv.sch b/atusd/sim/cdiv.sch
new file mode 100644
index 0000000..84269a5
--- /dev/null
+++ b/atusd/sim/cdiv.sch
@@ -0,0 +1,47 @@
+<Qucs Schematic 0.0.15>
+<Properties>
+  <View=0,-120,870,882,1,0,0>
+  <Grid=10,10,1>
+  <DataSet=cdiv.dat>
+  <DataDisplay=cdiv.dpl>
+  <OpenDisplay=1>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
+<Symbol>
+</Symbol>
+<Components>
+  <GND * 1 220 400 0 0 0 0>
+  <GND * 1 100 400 0 0 0 0>
+  <Vrect V1 1 100 310 18 -26 0 1 "3.3 V" 1 "31 ns" 1 "31 ns" 1 "1 ns" 0 "1 ns" 0 "0 ns" 0>
+  <.DC DC1 1 120 40 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
+  <.TR TR1 1 310 40 0 57 0 0 "lin" 1 "0" 1 "1 us" 1 "10000" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
+  <C C1 1 220 350 17 -26 0 1 "220 pF" 1 "" 0 "neutral" 0>
+  <R R1 1 150 200 -26 15 0 0 "50 Ohm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <C C2 1 220 250 17 -26 0 1 " 33 pF" 1 "" 0 "neutral" 0>
+</Components>
+<Wires>
+  <100 340 100 400 "" 0 0 0 "">
+  <220 280 220 320 "Vout" 250 270 17 "">
+  <220 380 220 400 "" 0 0 0 "">
+  <100 200 100 280 "" 0 0 0 "">
+  <100 200 120 200 "" 0 0 0 "">
+  <180 200 220 200 "" 0 0 0 "">
+  <220 200 220 220 "" 0 0 0 "">
+</Wires>
+<Diagrams>
+  <Rect 360 416 414 196 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+	<"Vout.Vt" #0000ff 0 3 0 0 0>
+  </Rect>
+  <Rect 360 683 421 203 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+	<"V1.It" #0000ff 0 3 0 0 0>
+  </Rect>
+  <Tab 530 210 300 200 3 #c0c0c0 1 00 1 923 1 1 1 0 1 1 1 0 1 10000 315 0 225 "" "" "">
+	<"Vout.Vt" #0000ff 0 3 1 0 0>
+  </Tab>
+</Diagrams>
+<Paintings>
+</Paintings>