From 86e556ce92af39a3353e0c6494ba20de59d47d4c Mon Sep 17 00:00:00 2001 From: Werner Almesberger Date: Sat, 4 Sep 2010 23:14:57 -0300 Subject: [PATCH] First part of the board bringup: power and clock. - atusd/ERRATA: variations of the circuit being debugged from the design - tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable the board and (in the future) establish communication - atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative load from scope probe --- atusd/ERRATA | 5 ++ atusd/sim/clk.sch | 54 +++++++++++++++++++ atusd/tools/Makefile | 7 +++ atusd/tools/lib/atusd.c | 113 ++++++++++++++++++++++++++++++++++++++++ atusd/tools/try.c | 14 +++++ 5 files changed, 193 insertions(+) create mode 100644 atusd/ERRATA create mode 100644 atusd/sim/clk.sch create mode 100644 atusd/tools/Makefile create mode 100644 atusd/tools/lib/atusd.c create mode 100644 atusd/tools/try.c diff --git a/atusd/ERRATA b/atusd/ERRATA new file mode 100644 index 0000000..88ec06a --- /dev/null +++ b/atusd/ERRATA @@ -0,0 +1,5 @@ +- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be + a bad trace. According to simulations, 22 pF should be more than enough. + +- added wire connecting uSD-side ground plane to ground plane at outer edge, + to improve CLK signal return. (Probably unnecessary, too.) diff --git a/atusd/sim/clk.sch b/atusd/sim/clk.sch new file mode 100644 index 0000000..c8a1960 --- /dev/null +++ b/atusd/sim/clk.sch @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + <.DC DC1 1 90 40 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0> + + <.TR TR1 1 100 120 0 57 0 0 "lin" 1 "0" 1 "0.1 us" 1 "9991" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0> + + + + + + + + + + <520 260 560 260 "" 0 0 0 ""> + <560 260 560 360 "" 0 0 0 ""> + <560 420 560 480 "" 0 0 0 ""> + <420 400 420 480 "" 0 0 0 ""> + <420 260 460 260 "" 0 0 0 ""> + <420 260 420 340 "" 0 0 0 ""> + <380 260 420 260 "Vmeas" 350 140 39 ""> + <280 360 280 400 "Vout" 170 330 17 ""> + <280 260 280 300 "" 0 0 0 ""> + <280 260 320 260 "" 0 0 0 ""> + <280 460 280 480 "" 0 0 0 ""> + <560 260 560 260 "Vin" 590 200 0 ""> + + + + <"Vin.Vt" #0000ff 0 3 0 0 0> + <"Vmeas.Vt" #ff0000 0 3 0 0 0> + <"Vout.Vt" #ff00ff 0 3 0 0 0> + + + <"Vout.Vt" #0000ff 0 3 0 0 0> + + + + diff --git a/atusd/tools/Makefile b/atusd/tools/Makefile new file mode 100644 index 0000000..c3c48a2 --- /dev/null +++ b/atusd/tools/Makefile @@ -0,0 +1,7 @@ +CC=mipsel-openwrt-linux-gcc +CFLAGS=-Wall + +MAIN = try +OBJS = $(MAIN).c lib/atusd.o + +$(MAIN): $(OBJS) diff --git a/atusd/tools/lib/atusd.c b/atusd/tools/lib/atusd.c new file mode 100644 index 0000000..210d6a0 --- /dev/null +++ b/atusd/tools/lib/atusd.c @@ -0,0 +1,113 @@ +#include +#include +#include +#include +#include + + +enum { + VDD_OFF = 1 << 6, /* VDD disable, PD06 */ + MxSx = 1 << 8, /* CMD, PD08 */ + CLK = 1 << 9, /* CLK, PD09 */ + SCLK = 1 << 10, /* DAT0, PD10 */ + SLP_TR = 1 << 11, /* DAT1, PD11 */ + IRQ = 1 << 12, /* DAT2, PD12 */ + nSEL = 1 << 13, /* DAT3/CD, PD13 */ +}; + + +#define SOC_BASE 0x10000000 + +#define REG(n) (*(volatile uint32_t *) (dsc->mem+(n))) + +#define CGU(n) REG(0x00000+(n)) +#define GPIO(n) REG(0x10000+(n)) +#define MSC(n) REG(0x21000+(n)) + +#define PDDATS GPIO(0x314) /* port D data set */ +#define PDDATC GPIO(0x318) /* port D data clear */ +#define PDFUNS GPIO(0x344) /* port D function set */ +#define PDFUNC GPIO(0x348) /* port D function clear */ +#define PDDIRS GPIO(0x364) /* port D direction set */ +#define PDDIRC GPIO(0x368) /* port D direction clear */ + +#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */ +#define MSC_CLKRT MSC(0x08) /* MSC Clock Rate */ + +#define CLKGR CGU(0x0020) /* Clock Gate */ +#define MSCCDR CGU(0x0068) /* MSC device clock divider */ + + +#define PAGE_SIZE 4096 + + +struct atusd_dsc { + int fd; + void *mem; +}; + + +struct atusd_dsc *atusd_open(void) +{ + struct atusd_dsc *dsc; + + dsc = malloc(sizeof(*dsc)); + if (!dsc) { + perror("malloc"); + exit(1); + } + + dsc->fd = open("/dev/mem", O_RDWR); + if (dsc->fd < 0) { + perror("/dev/mem"); + exit(1); + } + dsc->mem = mmap(NULL, PAGE_SIZE*3*16, PROT_READ | PROT_WRITE, + MAP_SHARED, dsc->fd, SOC_BASE); + if (dsc->mem == MAP_FAILED) { + perror("mmap"); + exit(1); + } + + /* set the output levels */ + PDDATS = nSEL | VDD_OFF; + PDDATC = SCLK | SLP_TR; + + /* take the GPIOs away from the MMC controller */ + PDFUNC = MxSx | SCLK | SLP_TR | IRQ | nSEL; + PDFUNS = CLK; + + /* set the pin directions */ + PDDIRC = IRQ; + PDDIRS = MxSx | CLK | SCLK | SLP_TR | nSEL; + + /* enable power */ + PDDATC = VDD_OFF; + + /* set the MSC clock to 316 MHz / 21 = 16 MHz */ + MSCCDR = 20; + /* + * Enable the MSC clock. We need to do this before accessing any + * registers of the MSC block ! + */ + CLKGR &= ~(1 << 7); + /* bus clock = MSC clock / 1 */ + MSC_CLKRT = 0; + /* start MMC clock output */ + MSC_STRPCL = 2; + + return dsc; +} + + +void atusd_close(struct atusd_dsc *dsc) +{ + /* stop the MMC clock */ + MSC_STRPCL = 1; + + /* cut the power */ + PDDATS = VDD_OFF; + + /* make all MMC pins inputs */ + PDDIRC = MxSx | CLK | SCLK | SLP_TR | IRQ | nSEL; +} diff --git a/atusd/tools/try.c b/atusd/tools/try.c new file mode 100644 index 0000000..d982fbe --- /dev/null +++ b/atusd/tools/try.c @@ -0,0 +1,14 @@ +struct atusd_dsc; + + +int main(void) +{ + struct atusd_dsc *dsc; + char tmp; + + dsc = atusd_open(); + read(1, tmp, 1); + atusd_close(dsc); + + return 0; +}