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git://projects.qi-hardware.com/ben-wpan.git
synced 2024-11-30 01:59:41 +02:00
atrf-txrx: added support for AT86RF231 continuous transmission mode
- atrf-txrx.c (test_mode): moved test mode setup to enter_test_mode_230 - atrf-txrx.c (enter_test_mode_231): enter test mode on AT86RF231 (untested) - atrf-txrx.c (test_mode): reset AT86RF231 register 0x1c when leaving
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@ -196,12 +196,11 @@ static void transmit(struct atrf_dsc *dsc, const char *msg, int times)
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}
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}
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static int test_mode(struct atrf_dsc *dsc, uint8_t cont_tx, const char *cmd)
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static void enter_test_mode_230(struct atrf_dsc *dsc, uint8_t cont_tx)
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{
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{
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atrf_buf_write(dsc, "", 1);
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atrf_buf_write(dsc, "", 1);
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atrf_reg_write(dsc, REG_CONT_TX_0, CONT_TX_MAGIC);
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atrf_reg_write(dsc, REG_CONT_TX_0, CONT_TX_MAGIC);
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atrf_reg_write(dsc, REG_CONT_TX_1, cont_tx);
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atrf_reg_write(dsc, REG_CONT_TX_1, cont_tx);
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int status = 0;
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if (!atrf_test_mode(dsc)) {
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if (!atrf_test_mode(dsc)) {
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atrf_reset_rf(dsc);
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atrf_reset_rf(dsc);
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@ -213,6 +212,64 @@ static int test_mode(struct atrf_dsc *dsc, uint8_t cont_tx, const char *cmd)
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wait_for_interrupt(dsc, IRQ_PLL_LOCK, IRQ_PLL_LOCK, 10, 20);
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wait_for_interrupt(dsc, IRQ_PLL_LOCK, IRQ_PLL_LOCK, 10, 20);
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_TX_START);
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_TX_START);
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}
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static void enter_test_mode_231(struct atrf_dsc *dsc, uint8_t cont_tx)
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{
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uint8_t buf[127];
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switch (cont_tx) {
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case CONT_TX_M2M:
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fprintf(stderr,
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"-2 MHz mode is not supported by the AT86RF231\n");
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break;
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case CONT_TX_M500K:
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memset(buf, 0, sizeof(buf));
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break;
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case CONT_TX_P500K:
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memset(buf, 0xff, sizeof(buf));
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break;
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default:
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abort();
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}
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atrf_reg_write(dsc, REG_IRQ_MASK, IRQ_PLL_LOCK); /* 2 */
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atrf_reg_write(dsc, REG_TRX_CTRL_1, 0); /* 3 */
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_FORCE_TRX_OFF); /* 4 */
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atrf_reg_write(dsc, REG_TRX_CTRL_0, CLKM_CTRL_1MHz); /* 5 */
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atrf_reg_read(dsc, REG_TRX_STATUS); /* 8 */
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atrf_reg_write(dsc, REG_CONT_TX_0, CONT_TX_MAGIC); /* 9 */
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atrf_reg_write(dsc, REG_TRX_CTRL_2, OQPSK_DATA_RATE_2000); /*10 */
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atrf_reg_write(dsc, REG_RX_CTRL, 0xa7); /*11 */
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atrf_buf_write(dsc, buf, sizeof(buf)); /*12 */
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atrf_reg_write(dsc, REG_PART_NUM, 0x54); /*13 */
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atrf_reg_write(dsc, REG_PART_NUM, 0x46); /*14 */
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_PLL_ON); /*15 */
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wait_for_interrupt(dsc, IRQ_PLL_LOCK, IRQ_PLL_LOCK, 10, 20); /*16 */
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_TX_START); /*17 */
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}
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static int test_mode(struct atrf_dsc *dsc, uint8_t cont_tx, const char *cmd)
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{
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int status = 0;
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switch (atrf_identify(dsc)) {
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case artf_at86rf230:
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enter_test_mode_230(dsc, cont_tx);
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break;
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case artf_at86rf231:
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enter_test_mode_231(dsc, cont_tx);
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break;
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default:
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abort();
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}
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if (cmd)
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if (cmd)
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status = system(cmd);
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status = system(cmd);
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@ -221,6 +278,9 @@ static int test_mode(struct atrf_dsc *dsc, uint8_t cont_tx, const char *cmd)
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sleep(1);
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sleep(1);
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}
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}
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if (atrf_identify(dsc) == artf_at86rf231)
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atrf_reg_write(dsc, REG_PART_NUM, 0);
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atrf_reset_rf(dsc);
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atrf_reset_rf(dsc);
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return status;
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return status;
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