diff --git a/atusb/fw/include/at86rf230.h b/atusb/fw/include/at86rf230.h
index 52aee26..a539f74 100644
--- a/atusb/fw/include/at86rf230.h
+++ b/atusb/fw/include/at86rf230.h
@@ -85,16 +85,11 @@ enum {
 	REG_CONT_TX_1		= 0x3d,
 };
 
-/* --- TRX_STATUS [7] ------------------------------------------------------ */
+/* --- TRX_STATUS --- ------------------------------------------------------ */
 
 #define	CCA_DONE	(1 << 7)
-
-/* --- TRX_STATUS [6] ------------------------------------------------------ */
-
 #define	CCA_STATUS	(1 << 6)
 
-/* --- TRX_STATUS [4:0] ---------------------------------------------------- */
-
 #define	TRX_STATUS_SHIFT	0
 #define	TRX_STATUS_MASK		0x1f
 
@@ -116,7 +111,7 @@ enum {
 	TRX_STATUS_TRANSITION		= 0x1f	/* ..._IN_PROGRESS */
 };
 
-/* --- TRX_STATE [7:5] ----------------------------------------------------- */
+/* --- TRX_STATE ----------------------------------------------------------- */
 
 #define	TRAC_STATUS_SHIFT	5
 #define	TRAC_STATUS_MASK	7
@@ -130,8 +125,6 @@ enum {
 	TRAC_STATUS_INVALID			= 7
 };
 
-/* --- TRX_STATE [4:0] ----------------------------------------------------- */
-
 #define	TRX_CMD_SHIFT	0
 #define	TRX_CMD_MASK	7
 
@@ -147,7 +140,7 @@ enum {
 	TRX_CMD_TX_ARET_ON	= 0x19,
 };
 
-/* --- TRX_CTRL_0 [7:6] ---------------------------------------------------- */
+/* --- TRX_CTRL_0 ---------------------------------------------------------- */
 
 #define	PAD_IO_SHIFT	6
 #define	PAD_IO_MASK	3
@@ -159,8 +152,6 @@ enum {
 	PAD_IO_8mA
 };
 
-/* --- TRX_CTRL_0 [5:4] ---------------------------------------------------- */
-
 #define	PAD_IO_CLKM_SHIFT	4
 #define	PAD_IO_CLKM_MASK	3
 
@@ -171,12 +162,8 @@ enum {
 	PAD_IO_CLKM_8mA,
 };
 
-/* --- TRX_CTRL_0 [3] ------------------------------------------------------ */
-
 #define	CLKM_SHA_SEL		(1 << 3)
 
-/* --- TRX_CTRL_0 [2:0] ---------------------------------------------------- */
-
 #define	CLKM_CTRL_SHIFT	0
 #define	CLKM_CTRL_MASK	3
 
@@ -208,39 +195,31 @@ enum {
 #define	IRQ_MASK_MODE		(1 << 1)
 #define	IRQ_POLARITY		(1 << 0)
 
-/* --- PHY_TX_PWR [7] ------------------------------------------------------ */
+/* --- PHY_TX_PWR -====----------------------------------------------------- */
 
 #define	TX_AUTO_CRC_ON		(1 << 7)	/* 230 */
 
-/* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */
-
 #define	TX_PWR_SHIFT	0
 #define	TX_PWR_MASK	0x0f
 
-/* --- PHY_RSSI [7] -------------------------------------------------------- */
+/* --- PHY_RSSI ------------------------------------------------------------ */
 
 #define	RX_CRC_VALID	(1 << 7)
 
-/* --- PHY_RSSI [4:0] ------------------------------------------------------ */
-
 #define	RSSI_SHIFT	0
 #define	RSSI_MASK	0x1f
 
-/* --- PHY_CC_CCA [7] ------------------------------------------------------ */
+/* --- PHY_CC_CCA ---------------------------------------------------------- */
 
 #define	CCA_REQUEST	(1 << 7)
 
-/* --- PHY_CC_CCA [6:5] ---------------------------------------------------- */
-
 #define	CCA_MODE_SHIFT	5
 #define	CCA_MODE_MASK	3
 
-/* --- PHY_CC_CCA [4:0] ---------------------------------------------------- */
-
 #define	CHANNEL_SHIFT	0
 #define	CHANNEL_MASK	0x1f
 
-/* --- CCA_THRES [3:0] ----------------------------------------------------- */
+/* --- CCA_THRES ----------------------------------------------------------- */
 
 #define	CCA_ED_THRES_SHIFT	0
 #define	CCA_ED_THRES_MASK	0x0f
@@ -256,24 +235,22 @@ enum {
 	IRQ_BAT_LOW	= 1 << 7
 };
 
-/* --- VREG_CTRL [7, 6, 3, 2] ---------------------------------------------- */
+/* --- VREG_CTRL ----------------------------------------------------------- */
 
 #define	AVREG_EXT	(1 << 7)
 #define	AVDD_OK		(1 << 6)
 #define	DVREG_EXT	(1 << 3)
 #define	DVDD_OK		(1 << 2)
 
-/* --- BATMON [5, 4] ------------------------------------------------------- */
+/* --- BATMON -------------------------------------------------------------- */
 
 #define	BATMON_OK	(1 << 5)
 #define	BATMON_HR	(1 << 4)
 
-/* --- BATMON [3:0] -------------------------------------------------------- */
-
 #define	NATMON_VTH_SHIFT	0
 #define	NATMON_VTH_MASK		0x0f
 
-/* --- XOSC_CTRL [7:4] ----------------------------------------------------- */
+/* --- XOSC_CTRL ----------------------------------------------------------- */
 
 #define	XTAL_MODE_SHIFT	4
 #define	XTAL_MODE_MASK	0x0f
@@ -284,49 +261,42 @@ enum {
 	XTAL_MODE_INT	= 0xf	/* reset default */
 };
 
-/* --- XOSC_CTRL [3:1] ----------------------------------------------------- */
-
 #define	XTAL_TRIM_SHIFT	4
 #define	XTAL_TRIM_MASK	0x0f
 
-/* --- XAH_CTRL [7:4] ------------------------------------------------------ */
+/* --- XAH_CTRL ------------------------------------------------------------ */
 
 #define	MAX_FRAME_RETRIES_SHIFT	4
 #define	MAX_FRAME_RETRIES_MASK	0x0f
+
 #define	MAX_CSMA_RETRIES_SHIFT	1
 #define	MAX_CSMA_RETRIES_MASK	0x07
 
-/* --- PLL_CF [7] ---------------------------------------------------------- */
+/* --- PLL_CF -------------------------------------------------------------- */
 
 #define	PLL_CF_START	(1 << 7)
 
-/* --- PLL_DCU [8] --------------------------------------------------------- */
+/* --- PLL_DCU ------------------------------------------------------------- */
 
 #define	PLL_DCU_START	(1 << 7)
 
-/* --- CSMA_SEED_1 [7:6] --------------------------------------------------- */
+/* --- CSMA_SEED_1 --------------------------------------------------------- */
 
 #define	MIN_BE_SHIFT		6
 #define	MIN_BE_MASK		3
 
-/* --- CSMA_SEED_1 [5] ----------------------------------------------------- */
-
 #define	AACK_SET_PD		(1 << 5)
 
-/* --- CSMA_SEED_1 [3] ----------------------------------------------------- */
-
 #define	I_AM_COORD		(1 << 3)
 
-/* --- CSMA_SEED_1 [2:0] --------------------------------------------------- */
-
 #define CSMA_SEED_1_SHIFT	0
 #define	CSMA_SEED_1_MASK	7
 
-/* --- REG_CONT_TX_0 [7:0] ------------------------------------------------- */
+/* --- REG_CONT_TX_0 ------------------------------------------------------- */
 
 #define	CONT_TX_MAGIC		0x0f
 
-/* --- REG_CONT_TX_1 [7:0] ------------------------------------------------- */
+/* --- REG_CONT_TX_1 ------------------------------------------------------- */
 
 #define	CONT_TX_MOD		0x00	/* modulated */
 #define	CONT_TX_M2M		0x10	/* f_CH-2 MHz */