From cdf3825d2461b7c4dde5f48c28ff87ffdc0d40c8 Mon Sep 17 00:00:00 2001 From: Werner Almesberger Date: Sat, 12 Mar 2011 23:43:00 -0300 Subject: [PATCH] atusb: added fab file generation, like in atben - Makefile (VERSION, DIR): added board version and parent directory name - Makefile: added generation of Gerbers and other fab files - Makefile (gen): this never worked, changed --plot to --plot=ps - Makefile: added section titles - README-PCB: PCB making instructions --- atusb/Makefile | 39 +++++++++++++++++++++++++++++++++++++-- atusb/README-PCB | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+), 2 deletions(-) create mode 100644 atusb/README-PCB diff --git a/atusb/Makefile b/atusb/Makefile index ccee54d..5378ab0 100644 --- a/atusb/Makefile +++ b/atusb/Makefile @@ -1,15 +1,18 @@ PLOT_BRD = pcbnew --plot=ps_a4 --ps-pads-drill-opt=none --fill-all-zones NAME = atusb +VERSION = 110214 +DIR = $(NAME) .PHONY: all gen generate sch brd xpdf front back clean +.PHONY: gerber gerbv fab all: @echo "make what ? target: gen sch brd xpdf front back clean" @exit 1 gen generate: - eeschema --plot `pwd`/$(NAME).sch + eeschema --plot=ps `pwd`/$(NAME).sch # need scripts sch: @@ -27,6 +30,8 @@ front: $(NAME)-Front.ps back: $(NAME)-Back.ps lpr $< +# --- DIY production (toner transfer) ----------------------------------------- + # # Postscript for production of front/back layer, using the toner transfer # method. Note that other artwork transfer methods may require different @@ -44,9 +49,39 @@ back: $(NAME)-Back.ps %-Back.ps: %.brd $(PLOT_BRD) -l Back $< +# --- Industrial production --------------------------------------------------- + +PCB_FILES = README-PCB $(NAME)-PCB_Edges.dxf $(NAME).drl \ + $(NAME)-SilkS_Front.gto $(NAME)-Mask_Front.gts \ + $(NAME)-Front.gtl $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs \ + $(NAME)-PCB_Edges.gbr + +gerber: + pcbnew --plot=gerber \ + -l `pcbnew --list-layers $(NAME).brd | tr '\012' ,` \ + --fill-all-zones $(NAME).brd \ + --exclude-pcb-edge + +fab: gerber + pcbnew --plot=dxf -l PCB_Edges $(NAME).brd + pcbnew --drill $(NAME).brd + tar Ccfz .. $(NAME)-$(VERSION).tar.gz $(PCB_FILES:%=$(DIR)/%) + cd ..; zip -l $(DIR)/$(NAME)-$(VERSION).zip \ + $(PCB_FILES:%=$(DIR)/%) + +gerbv: + gerbv $(NAME)-Comments.gbr \ + $(NAME)-SilkS_Front.gto \ + $(NAME)-SoldP_Front.gtp \ + $(NAME)-Front.gtl \ + $(NAME)-Mask_Front.gts \ + $(NAME)-Back.gbl + +# --- Cleanup ----------------------------------------------------------------- + clean: rm -f $(NAME)-Front.ps $(NAME)-Back.ps - rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr + rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr $(NAME)-PCB_Edges.dxf rm -f $(NAME)-Front.gtl $(NAME)-Mask_Front.gts rm -f $(NAME)-SilkS_Front.gto $(NAME)-SoldP_Front.gtp rm -f $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs diff --git a/atusb/README-PCB b/atusb/README-PCB new file mode 100644 index 0000000..1c82a1c --- /dev/null +++ b/atusb/README-PCB @@ -0,0 +1,38 @@ +Board characteristics: + +- stacking: 2 layers, solder mask on front and back, silk screen on front +- board material: FR4, thickness 0.8 mm, 1 oz copper +- surface finish: TBD, both ENIG and tin are acceptable +- via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used +- mechanical tolerances: <= +/- 0.1 mm on all sides + +Layer stacking, from top to bottom: + +atusb-SilkS_Front.gto Front silk screen +atusb-Mask_Front.gts Front solder mask +atusb-Front.gtl Front copper +atusb-Back.gbl Back copper +atusb-Mask_Back.gbs Back solder mask (empty) + +Other design files: + +atusb-PCB_Edges.gbr Board edges, for routing (Gerber) +atusb.dxf idem (AutoCAD DXF) +atusb.drl Excellon drill file + +Interpretation of files: + +- do not print PCB edges on front/back copper +- do not print component values on silk screen +- the center (!) of the board edge line marks the true board edge, e.g., + + Edge line (5 mil) + ======= + ------- - - - - - ---------- + | | + PCB outside | | PCB inside + | | + ------- - - - - - ---------- + | + Volume removed when cutting + (width depends on tool used)