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New ECN about clock circuit of atusd boards. Measured (absence of) effect of
adding an inductor to the clock line. - ecn/INDEX, ecn/ecn0005.txt: new ECN discussing the switch to a capacitative clock voltage divider. With frequency measurements. - atusd/tests/send-20100910: measurement of transceiver performance when placing an inductor in the 16 MHz clock line.
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atusd/tests/send-20100910
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66
atusd/tests/send-20100910
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Same test setup as for send-20100909. Board 100908-A was modified to have
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a 220 nH inductor in the C7 position, instead of a 0R resistor.
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Distant Local
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--------------- --------------- ---------------
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100813-red 100813-orange 100908-A (with inductor)
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TX 255, -91 255, -85
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TX 255, -90 255, -85
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TX 255, -91 -
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TX 255, -90 255, -85
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TX 255, -91 garbled
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- TX 255, -47
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- TX 255, -47
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- TX 255, -47
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- TX 255, -47
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garbled (-90) TX 255, -47
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255, -82 255, -43 TX
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255, -82 255, -43 TX
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255, -82 255, -43 TX
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255, -82 255, -43 TX
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255, -82 255, -43 TX
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Control experiment:
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100813-red 100813-orange 100908-B (unmodified)
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TX - 255, -83
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TX garbled (-91) 255, -86
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TX - 255, -86
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TX garbled (-91) 255, -86
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TX - 255, -86
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255, -83 255, -43 TX
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255, -84 255, -43 TX
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255, -85 255, -43 TX
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255, -84 255, -43 TX
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255, -84 255, -43 TX
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Summary
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-------
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Direction No inductor (1) With ind. (2) Change
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------------------------------- --------------- ------------ ------
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100813-red -> 100813-orange 255, -87 255, -91 -4 dB
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100813-red -> 100908-A 255, -88 255, -85 +3 dB
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100908-A -> 100813-red 255, -85 255, -82 +3 dB
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100813-red -> 100813-orange 255, -90 - ?
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100813-red -> 100908-B 255, -90 255, -86 +4 dB
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100908-B -> 100813-red 255, -87 255, -84 +3 dB
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(1) Data from send-20100909
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(2) Only 100908-A was modified. Changes in the measurements with
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100908-B show inaccuracies of the test setup.
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Conclusion
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----------
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The differences observed are the same for the modified 100908-A board
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and the unmodified 100908-B board. The inductor therefore does not seem
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to have a significant effect on transceiver performance.
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@ -4,3 +4,4 @@ Number Status Description
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0002 Done Add load capacitors to 16 MHz crystal
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0002 Done Add load capacitors to 16 MHz crystal
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0003 Edit Replace balun and filter with integrated balun
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0003 Edit Replace balun and filter with integrated balun
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0004 Edit Take into account layout considerations for RF
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0004 Edit Take into account layout considerations for RF
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0005 Edit Correct atusd clock voltage divider
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37
ecn/ecn0005.txt
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37
ecn/ecn0005.txt
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Correct atusd clock voltage divider
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According to section 9.6.3 of the data sheet, an external clock supplied
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to the AT86RF230 has a minimum peak-to-peak voltage of 400 mV and a
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maximum of only 500 mV. Furthermore, the signal must be DC-free.
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The voltage divider in the 20100903 and 20100908 designs is too sensitive
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to interference and the PLL constantly unlocks, rendering the device
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dysfunctional.
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A more robust divider circuit can be obtained with the following
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replacements: C7 -> 0R, R3 -> 33 pF, R4 -> 220 pF. After reworking the
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20100908 boards, they no longer suffer PLL unlocks.
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A Qucs simulation of the circuit can be found in ../atusd/sim/cdiv.sim
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Frequency measurements yield the following results:
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Host Board Error Meas. accuracy
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(f, ppm) (ppm, nom.)
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------- --------------- --------------- ---------------
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Ben #2 20100908-A +2 99.7
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+1 99.6
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Ben #1 20100908-A +23 99.7
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+24 99.9
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Ben #1 20100908-B +24 99.4
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+24 99.7
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Ben #2 20100908-B +2 99.8
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+2 99.9
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The Ben's 12 MHz crystal has a tolerance of +/- 30 ppm, which is better
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than the +/- 40 ppm required by IEEE 802.15.4.
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What remains to be verified is whether this change causes interferences
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that may affect transceiver performance and may also violate emission
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regulations.
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