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New ECN about clock circuit of atusd boards. Measured (absence of) effect of

adding an inductor to the clock line.

- ecn/INDEX, ecn/ecn0005.txt: new ECN discussing the switch to a
  capacitative clock voltage divider. With frequency measurements.
- atusd/tests/send-20100910: measurement of transceiver performance when
  placing an inductor in the 16 MHz clock line.
This commit is contained in:
Werner Almesberger 2010-09-10 00:06:33 -03:00
parent d3bc274dab
commit df071c3398
3 changed files with 104 additions and 0 deletions

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atusd/tests/send-20100910 Normal file
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Same test setup as for send-20100909. Board 100908-A was modified to have
a 220 nH inductor in the C7 position, instead of a 0R resistor.
Distant Local
--------------- --------------- ---------------
100813-red 100813-orange 100908-A (with inductor)
TX 255, -91 255, -85
TX 255, -90 255, -85
TX 255, -91 -
TX 255, -90 255, -85
TX 255, -91 garbled
- TX 255, -47
- TX 255, -47
- TX 255, -47
- TX 255, -47
garbled (-90) TX 255, -47
255, -82 255, -43 TX
255, -82 255, -43 TX
255, -82 255, -43 TX
255, -82 255, -43 TX
255, -82 255, -43 TX
Control experiment:
100813-red 100813-orange 100908-B (unmodified)
TX - 255, -83
TX garbled (-91) 255, -86
TX - 255, -86
TX garbled (-91) 255, -86
TX - 255, -86
255, -83 255, -43 TX
255, -84 255, -43 TX
255, -85 255, -43 TX
255, -84 255, -43 TX
255, -84 255, -43 TX
Summary
-------
Direction No inductor (1) With ind. (2) Change
------------------------------- --------------- ------------ ------
100813-red -> 100813-orange 255, -87 255, -91 -4 dB
100813-red -> 100908-A 255, -88 255, -85 +3 dB
100908-A -> 100813-red 255, -85 255, -82 +3 dB
100813-red -> 100813-orange 255, -90 - ?
100813-red -> 100908-B 255, -90 255, -86 +4 dB
100908-B -> 100813-red 255, -87 255, -84 +3 dB
(1) Data from send-20100909
(2) Only 100908-A was modified. Changes in the measurements with
100908-B show inaccuracies of the test setup.
Conclusion
----------
The differences observed are the same for the modified 100908-A board
and the unmodified 100908-B board. The inductor therefore does not seem
to have a significant effect on transceiver performance.

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@ -4,3 +4,4 @@ Number Status Description
0002 Done Add load capacitors to 16 MHz crystal 0002 Done Add load capacitors to 16 MHz crystal
0003 Edit Replace balun and filter with integrated balun 0003 Edit Replace balun and filter with integrated balun
0004 Edit Take into account layout considerations for RF 0004 Edit Take into account layout considerations for RF
0005 Edit Correct atusd clock voltage divider

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Correct atusd clock voltage divider
According to section 9.6.3 of the data sheet, an external clock supplied
to the AT86RF230 has a minimum peak-to-peak voltage of 400 mV and a
maximum of only 500 mV. Furthermore, the signal must be DC-free.
The voltage divider in the 20100903 and 20100908 designs is too sensitive
to interference and the PLL constantly unlocks, rendering the device
dysfunctional.
A more robust divider circuit can be obtained with the following
replacements: C7 -> 0R, R3 -> 33 pF, R4 -> 220 pF. After reworking the
20100908 boards, they no longer suffer PLL unlocks.
A Qucs simulation of the circuit can be found in ../atusd/sim/cdiv.sim
Frequency measurements yield the following results:
Host Board Error Meas. accuracy
(f, ppm) (ppm, nom.)
------- --------------- --------------- ---------------
Ben #2 20100908-A +2 99.7
+1 99.6
Ben #1 20100908-A +23 99.7
+24 99.9
Ben #1 20100908-B +24 99.4
+24 99.7
Ben #2 20100908-B +2 99.8
+2 99.9
The Ben's 12 MHz crystal has a tolerance of +/- 30 ppm, which is better
than the +/- 40 ppm required by IEEE 802.15.4.
What remains to be verified is whether this change causes interferences
that may affect transceiver performance and may also violate emission
regulations.