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atusb/fw2: autonomously restore the clock output settings after an RF reset

Browse Source 
- atusb.c (main), board.c (set_clkm): moved CLKM initialization to
  board.c
- board.c (reset_rf): initialize the CLKM after each transceiver reset
This commit is contained in:
Werner Almesberger 2011-02-10 10:05:38 -03:00
parent 3e9f9613cb
commit e8b68041a5
2 changed files with 25 additions and 16 deletions
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16
atusb/fw2/atusb.c
View File

@ -7,7 +7,6 @@
#include "freakusb.h" #include "freakusb.h"
#include "at86rf230.h"
#include "board.h" #include "board.h"
#include "spi.h" #include "spi.h"
#include "atusb/ep0.h" #include "atusb/ep0.h"
@ -30,21 +29,6 @@ int main(void)
reset_rf(); reset_rf();
/* switch CLKM to 8 MHz */
/*
* @@@ Note: Atmel advise against changing the external clock in
* mid-flight. We should therefore switch to the RC clock first, then
* crank up the external clock, and finally switch back to the external
* clock. The clock switching procedure is described in the ATmega32U2
* data sheet in secton 8.2.2.
*/
spi_begin();
spi_send(AT86RF230_REG_WRITE | REG_TRX_CTRL_0);
spi_send(CLKM_CTRL_8MHz);
spi_end();
/* now we should be at 8 MHz */ /* now we should be at 8 MHz */
SET(LED); SET(LED);

25
atusb/fw2/board.c
View File

@ -5,7 +5,28 @@
#define F_CPU 8000000UL #define F_CPU 8000000UL
#include <util/delay.h> #include <util/delay.h>
#include "at86rf230.h"
#include "board.h" #include "board.h"
#include "spi.h"
static void set_clkm(void)
{
/* switch CLKM to 8 MHz */
/*
* @@@ Note: Atmel advise against changing the external clock in
* mid-flight. We should therefore switch to the RC clock first, then
* crank up the external clock, and finally switch back to the external
* clock. The clock switching procedure is described in the ATmega32U2
* data sheet in secton 8.2.2.
*/
spi_begin();
spi_send(AT86RF230_REG_WRITE | REG_TRX_CTRL_0);
spi_send(CLKM_CTRL_8MHz);
spi_end();
}
void reset_rf(void) void reset_rf(void)
@ -19,6 +40,10 @@ void reset_rf(void)
/* 12.4.14: SPI access latency after reset: 625 ns (min) */ /* 12.4.14: SPI access latency after reset: 625 ns (min) */
_delay_us(1); _delay_us(1);
/* we must restore TRX_CTRL_0 after each reset (9.6.4) */
set_clkm();
} }