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Commit Graph

2 Commits

Author SHA1 Message Date
Werner Almesberger
6e726d1fb9 Improved clock stability by using a capacitative divider and found more minor
issues.

- atusd/ERRATA: work around the clock instability by replacing the
  resistive divider with a capacitative divider
- atusd/ERRATA: a ground plane under the clock circuit would also be good to
  have
- atusd/ERRATA: via near pin 1 is too close to the chip if we need to cut
  wires (in DIY boards)
- atusd/sim/cdiv.sch: simulation of the capacitative divider
2010-09-09 12:35:47 -03:00
Werner Almesberger
86e556ce92 First part of the board bringup: power and clock.
- atusd/ERRATA: variations of the circuit being debugged from the design
- tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable
  the board and (in the future) establish communication
- atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative
  load from scope probe
2010-09-04 23:14:57 -03:00