- atusb.brd: increased RF ground zone by 150 mil in an attempt to reduce
interferences between the the antenna and the rest of the circuit
- atusb.brd: added more vias around and inside the RF ground zone
- atusb.brd: set version to 20110102
Traces leaving a pad on the side may invite solder bridges to "false pads"
exposed at the edges of the chip, with unknown consequences.
- atusb.brd: make trace from P0.0 (IRQ_RF) leave pad at the front, not
at the side
- atusb.brd: make trave from P0.7 (SCLK) leave pad at front, not at the
side
- atusb.brd: nRST may need an external pull-up to VDD. Added via to bring
nRST and VDD within reach (pull-up suggested by Joerg Reisenweber)
- atusb.brd: increased version to 20101229
- atusb.brd: increase clearance between RF clock front ground area and MCU
(ground area acted as solder trap)
- atusb.brd: route nRST_RF trace out of corner (to avoid accidental
contact)
- atusb.brd: don't route VBUS corner trace underneat chip (for general
tidiness)
- atusb.brd: bumped version to 20101219
- atusb.brd: reduced RF front ground area to avoid interconnections very
close to the chip
- atusb.brd: reduced RF power front ground area to avoid interconnections
very close to the chip
- atusb.brd: moved via next to TXRX pad 18 (GND) to make room for making
CLK trace leave the pad at its end, not at its side
- atusb.brd: bumped design date to 20101217
- fw/Makefile: replaced "make" with $(MAKE) (just for style)
- common/Makefile.common: Makefile settings shared within project. For now,
this contains only the board version, which defaults to 2010-12-16.
- fw/common/Makefile, fw/boot/Makefile, fw/atusb/Makefile: include
common/Makefile.common
- fw/common/Makefile, fw/boot/Makefile, fw/atusb/Makefile: pass board
version to cpp and gcc
- fw/atusb/atusb.c (init_io): individually set IRQ_RF to one, LED and TST
to zero
- fw/atusb/atusb.c (init_io): added macros to set all unused pins to zero
in a way that doesn't need updating if a signal moves from one pin to
another
- include/atusb/ep0.h: added hardware type 1 (2010-12-16 design)
- common/config.h: set hardware type depending on board version
- common/io.h: assign pins depending on board version
- atusb/cam2/mkmk: updated for new board
- atusb/cam2/mkmk: further increased board to board spacing, to reduce
board deflection
- atusb/cam2/mkmk: decreased nominal mill diameter to 20 mil to compensate
for board/tool deflection
- atusb/cam2/mkmk: added target "dplot" to visualize the sequence in which
holes are drilled
- mkmk: adjust board position
- mkmk: reorder output such that the edge is cut last, reducing board shift
- mkmk: reduce nominal mill diameter for large holes and slots, to increase
hole/slot size
- mkmk: generate "plot" target in Makefile, to visualize the output
- mkmk: use toolpath file for "cngt" instead of calculating the reference
point manually
Run ./mkmk to generate toolpaths and a Makefile. Then
make cng changes tools (used for drill and mill)
make drill does the drilling
make mill does the milling
- usb.sch: use P0.2 as board revision ID pin
- atrf.sch: label feed line
- atusb.brd: set feed line width via design rule, not as user size
- atusb.brd: increase feed line width from 18 mil to 19 mil (it should be
58 mil, but we don't have room for more)
- atusb.brd: bumped version number to 20101202
- atusb.brd: put version number on PCB
- atusb.sch, usb.sch, atrf.sch: bumped version number to 20101202
- atusb.brd: moved traces into USB plug such that they coincide with
thermal relief
- atusb.brd: moved trace into antenna ground such that it coincides
with thermal relief
- atusb.pro: reduced edge and drawing line width from 15 mil to 5 mil
- atusb.brd: added ground zones on bottom layer
- atusb.brd: moved IRQ_RF and VDD traces for better ground area coverage
- atusb.brd: move antenna to its rightful place
- atusb.brd: added two more GND vias after antenna move
- atusb.brd: added proper board edge
- atusb.brd: added board dimensions (16.3 x 33.2 mm)
- atusb.brd: moved via next to C11 closer to C11 and away from RF section
- atusb/atusb.pro: instead of modules/meander, use experimental ants/meander
- atusb/atusb.pro: typo - it's modules/usb_a_plug_smt, not
modules/usb_a_plug
- atusb/atusb.cmp (ANT1): change antenna from "meander" to "MEANDER-110"
(10% enlarged)
- atusb/atusb.cmp (CON1): change from "miniUSB_B" USB receptacle to
"USB-A-PLUG-SMT" plug
- atusb/atusb.cmp (VR1, VR2, VR3): update value from schematics
Examples:
doall 'run/*' # no arguments
doall -o foo.png 'run/*' # arguments for plscan
doall -a 1 -- -o foo.png 'run/*' # arguments for evscan and plscan
- usrp/doall: added usage()
- usrp/doall: arguments before -- are passed to evscan
We now have a much wider dynamic range of the signal (with better SNR).
The outliers are mainly WLAN interferences.
- usrp/evscan: changed threshold from -50 dB to -70 dB
- usrp/evscan: increase outlier tolerance from 2 dB to 10 dB
- usrp/plscan: changed display range from [-35:-25] to [-40:-5]
- ants/cam/doit: coordinates for new workpiece
- ants/cam/pcb.pl: new margins (specific to workpiece)
- ants/cam/pcb.pl: changed width and slot (specific to board being cut)
