mirror of
git://projects.qi-hardware.com/ben-wpan.git
synced 2024-07-05 05:47:40 +03:00
309a5ed6d5
- at86rf230.h (TX_AUTO_CRC_ON): changed to TX_AUTO_CRC_ON_230 - at86rf230.h (TX_AUTO_CRC_ON_231): changed to TX_AUTO_CRC_ON - tools/atrf-txrx/atrf-txrx.c: updated for above changes
403 lines
9.5 KiB
C
403 lines
9.5 KiB
C
/*
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* include/at86rf230.h - AT86RF230/AT86RF231 protocol and register definitions
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*
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* Written 2008-2011 by Werner Almesberger
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* Copyright 2008-2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT86RF230_H
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#define AT86RF230_H
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enum {
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AT86RF230_REG_WRITE = 0xc0, /* 11... */
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AT86RF230_REG_READ = 0x80, /* 10... */
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AT86RF230_BUF_WRITE = 0x60, /* 011... */
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AT86RF230_BUF_READ = 0x20, /* 001... */
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AT86RF230_SRAM_WRITE = 0x40, /* 010... */
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AT86RF230_SRAM_READ = 0x00 /* 000... */
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};
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#define MAX_PSDU 127 /* octets, see AT86RF230 manual section 8.1 */
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#define SRAM_SIZE 128
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/* --- Registers ----------------------------------------------------------- */
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enum {
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REG_TRX_STATUS = 0x01,
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REG_TRX_STATE = 0x02,
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REG_TRX_CTRL_0 = 0x03,
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REG_TRX_CTRL_1 = 0x04, /* 231 only */
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REG_PHY_TX_PWR = 0x05,
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REG_PHY_RSSI = 0x06,
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REG_PHY_ED_LEVEL = 0x07,
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REG_PHY_CC_CCA = 0x08,
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REG_CCA_THRES = 0x09,
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REG_RX_CTRL = 0x0a, /* 231 only */
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REG_SFD_VALUE = 0x0b, /* 231 only */
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REG_TRX_CTRL_2 = 0x0c, /* 231 only */
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REG_ANT_DIV = 0x0d, /* 231 only */
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REG_IRQ_MASK = 0x0e,
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REG_IRQ_STATUS = 0x0f,
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REG_VREG_CTRL = 0x10,
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REG_BATMON = 0x11,
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REG_XOSC_CTRL = 0x12,
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REG_RX_SYN = 0x15, /* 231 only */
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REG_XAH_CTRL_1 = 0x17, /* 231 only */
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REG_FTN_CTRL = 0x18, /* 231 only */
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REG_PLL_CF = 0x1a,
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REL_PLL_DCU = 0x1b,
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REG_PART_NUM = 0x1c,
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REG_VERSION_NUM = 0x1d,
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REG_MAN_ID_0 = 0x1e,
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REG_MAN_ID_1 = 0x1f,
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REG_SHORT_ADDR_0 = 0x20,
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REG_SHORT_ADDR_1 = 0x21,
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REG_PAN_ID_0 = 0x22,
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REG_PAN_ID_1 = 0x23,
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REG_IEEE_ADDR_0 = 0x24,
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REG_IEEE_ADDR_1 = 0x25,
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REG_IEEE_ADDR_2 = 0x26,
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REG_IEEE_ADDR_3 = 0x27,
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REG_IEEE_ADDR_4 = 0x28,
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REG_IEEE_ADDR_5 = 0x29,
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REG_IEEE_ADDR_6 = 0x2a,
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REG_IEEE_ADDR_7 = 0x2b,
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REG_XAH_CTRL_0 = 0x2c, /* XAH_CTRL in 230 */
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REG_CSMA_SEED_0 = 0x2d,
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REG_CSMA_SEED_1 = 0x2e,
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REG_CSMA_BE = 0x2f, /* 231 only */
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REG_CONT_TX_0 = 0x36,
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REG_CONT_TX_1 = 0x3d, /* 230 only */
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};
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/* --- TRX_STATUS --- ------------------------------------------------------ */
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#define CCA_DONE (1 << 7)
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#define CCA_STATUS (1 << 6)
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#define TRX_STATUS_SHIFT 0
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#define TRX_STATUS_MASK 0x1f
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enum {
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TRX_STATUS_P_ON = 0x00, /* reset default */
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TRX_STATUS_BUSY_RX = 0x01,
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TRX_STATUS_BUSY_TX = 0x02,
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TRX_STATUS_RX_ON = 0x06,
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TRX_STATUS_TRX_OFF = 0x08,
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TRX_STATUS_PLL_ON = 0x09,
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TRX_STATUS_SLEEP = 0x0f,
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TRX_STATUS_BUSY_RX_AACK = 0x11,
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TRX_STATUS_BUSY_TX_ARET = 0x12,
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TRX_STATUS_RX_AACK_ON = 0x16,
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TRX_STATUS_TX_ARET_ON = 0x19,
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TRX_STATUS_RX_ON_NOCLK = 0x1c,
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TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d,
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TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e,
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TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */
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};
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/* --- TRX_STATE ----------------------------------------------------------- */
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#define TRAC_STATUS_SHIFT 5
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#define TRAC_STATUS_MASK 7
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enum {
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TRAC_STATUS_SUCCESS = 0, /* reset default */
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TRAC_STATUS_SUCCESS_DATA_PENDING = 1,
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TRAC_STATUS_SUCCESS_WAIT_FOR_ACK = 2, /* 231 only */
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TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3,
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TRAC_STATUS_NO_ACK = 5,
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TRAC_STATUS_INVALID = 7
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};
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#define TRX_CMD_SHIFT 0
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#define TRX_CMD_MASK 0x1f
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enum {
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TRX_CMD_NOP = 0x00, /* reset default */
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TRX_CMD_TX_START = 0x02,
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TRX_CMD_FORCE_TRX_OFF = 0x03,
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TRX_CMD_FORCE_PLL_ON = 0x04, /* 231 only */
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TRX_CMD_RX_ON = 0x06,
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TRX_CMD_TRX_OFF = 0x08,
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TRX_CMD_PLL_ON = 0x09,
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TRX_CMD_RX_AACK_ON = 0x16,
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TRX_CMD_TX_ARET_ON = 0x19,
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};
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/* --- TRX_CTRL_0 ---------------------------------------------------------- */
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#define PAD_IO_SHIFT 6
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#define PAD_IO_MASK 3
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enum {
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PAD_IO_2mA, /* reset default */
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PAD_IO_4mA,
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PAD_IO_6mA,
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PAD_IO_8mA
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};
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#define PAD_IO_CLKM_SHIFT 4
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#define PAD_IO_CLKM_MASK 3
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enum {
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PAD_IO_CLKM_2mA,
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PAD_IO_CLKM_4mA, /* reset default */
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PAD_IO_CLKM_5mA,
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PAD_IO_CLKM_8mA,
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};
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#define CLKM_SHA_SEL (1 << 3)
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#define CLKM_CTRL_SHIFT 0
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#define CLKM_CTRL_MASK 7
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enum {
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CLKM_CTRL_OFF = 0,
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CLKM_CTRL_1MHz = 1, /* reset default */
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CLKM_CTRL_2MHz = 2,
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CLKM_CTRL_4MHz = 3,
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CLKM_CTRL_8MHz = 4,
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CLKM_CTRL_16MHz = 5
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};
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/* --- TRX_CTRL_1 (231 only) ----------------------------------------------- */
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#define PA_EXT_EN (1 << 7)
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#define IRQ_2_EXT_EN (1 << 6)
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#define TX_AUTO_CRC_ON (1 << 5) /* 231 location */
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#define RX_BL_CTRL (1 << 4)
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#define SPI_CMD_MODE_SHIFT 2
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#define SPI_CMD_MODE_MASK 3
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enum {
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SPI_CMD_MODE_EMPTY = 0, /* reset default */
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SPI_CMD_MODE_TRX_STATUS = 1,
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SPI_CMD_MODE_PHY_RSSI = 2,
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SPI_CMD_MODE_IRQ_STATUS = 3,
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};
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#define IRQ_MASK_MODE (1 << 1)
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#define IRQ_POLARITY (1 << 0)
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/* --- PHY_TX_PWR ---------------------------------------------------------- */
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#define TX_AUTO_CRC_ON_230 (1 << 7) /* 230 location */
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#define PA_BUF_LT_SHIFT 6
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#define PA_BUF_LT_MASK 3
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#define PA_LT_SHIFT 4
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#define PA_LT_MASK 3
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#define TX_PWR_SHIFT 0
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#define TX_PWR_MASK 0x0f
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/* --- PHY_RSSI ------------------------------------------------------------ */
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#define RX_CRC_VALID (1 << 7)
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#define RND_VALUE_SHIFT 5 /* 231 only */
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#define RND_VALUE_MASK 3
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#define RSSI_SHIFT 0
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#define RSSI_MASK 0x1f
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/* --- PHY_CC_CCA ---------------------------------------------------------- */
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#define CCA_REQUEST (1 << 7)
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#define CCA_MODE_SHIFT 5
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#define CCA_MODE_MASK 3
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enum {
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CCA_MODE_CARRIER_OR_ENERGY = 0, /* 231 only */
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CCA_MODE_ENERGY = 1, /* reset default */
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CCA_MODE_CARRIER = 2,
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CCA_MODE_CARRIER_AND_ENERGY = 3
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};
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#define CHANNEL_SHIFT 0
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#define CHANNEL_MASK 0x1f
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/* --- CCA_THRES ----------------------------------------------------------- */
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#define CCA_ED_THRES_SHIFT 0
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#define CCA_ED_THRES_MASK 0x0f
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/* --- RX_CTRL (231 only) -------------------------------------------------- */
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#define PDT_THRES_SHIFT 0
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#define PDT_THRES_MASK 0x0f
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enum {
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PDT_THRES_DEFAULT = 0x07, /* reset default */
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PDT_THRES_DIVERSITY = 0x03,
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};
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/* --- TRX_CTRL_2 (231 only) ----------------------------------------------- */
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#define RX_SAFE_MODE (1 << 7)
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#define OQPSK_DATA_RATE_SHIFT 0
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#define OQPSK_DATA_RATE_MASK 3
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enum {
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OQPSK_DATA_RATE_250 = 0, /* reset default */
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OQPSK_DATA_RATE_500 = 1,
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OQPSK_DATA_RATE_1000 = 2,
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OQPSK_DATA_RATE_2000 = 3
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};
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/* --- ANT_DIV (231 only) -------------------------------------------------- */
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#define ANT_SEL (1 << 7)
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#define ANT_DIV_EN (1 << 3)
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#define ANT_EXT_SW_EN (1 << 2)
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#define ANT_CTRL_SHIFT 0
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#define ANT_CTRL_MASK 3
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enum {
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ANT_CTRL_ANT_0 = 1,
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ANT_CTRL_ANT_1 = 2,
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ANT_CTRL_NODIV = 3, /* reset default */
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};
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/* --- IRQ_MASK/IRQ_STATUS ------------------------------------------------- */
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enum {
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IRQ_PLL_LOCK = 1 << 0,
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IRQ_PLL_UNLOCK = 1 << 1,
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IRQ_RX_START = 1 << 2,
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IRQ_TRX_END = 1 << 3,
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IRQ_CCA_ED_DONE = 1 << 4, /* 231 only */
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IRQ_AMI = 1 << 5, /* 231 only */
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IRQ_TRX_UR = 1 << 6,
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IRQ_BAT_LOW = 1 << 7
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};
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/* --- VREG_CTRL ----------------------------------------------------------- */
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#define AVREG_EXT (1 << 7)
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#define AVDD_OK (1 << 6)
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#define DVREG_EXT (1 << 3)
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#define DVDD_OK (1 << 2)
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/* --- BATMON -------------------------------------------------------------- */
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#define BATMON_OK (1 << 5)
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#define BATMON_HR (1 << 4)
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#define BATMON_VTH_SHIFT 0
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#define BATMON_VTH_MASK 0x0f
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/* --- XOSC_CTRL ----------------------------------------------------------- */
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#define XTAL_MODE_SHIFT 4
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#define XTAL_MODE_MASK 0x0f
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enum {
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XTAL_MODE_OFF = 0x0, /* 230 only */
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XTAL_MODE_EXT = 0x4,
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XTAL_MODE_INT = 0xf /* reset default */
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};
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#define XTAL_TRIM_SHIFT 4
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#define XTAL_TRIM_MASK 0x0f
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/* --- RX_SYN (231 only) --------------------------------------------------- */
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#define RX_PDT_DIS (1 << 7)
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#define RX_PDT_LEVEL_SHIFT 0
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#define RX_PDT_LEVEL_MASK 0xf
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/* --- XAH_CTRL_1 (231 only) ----------------------------------------------- */
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#define AACK_FLTR_RES_FT (1 << 5)
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#define AACK_UPLD_RES_FT (1 << 4)
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#define AACK_ACK_TIME (1 << 2)
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#define AACK_PROM_MODE (1 << 1)
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/* --- FTN_CTRL (231 only) ------------------------------------------------- */
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#define FTN_START (1 << 7)
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/* --- PLL_CF -------------------------------------------------------------- */
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#define PLL_CF_START (1 << 7)
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/* --- PLL_DCU ------------------------------------------------------------- */
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#define PLL_DCU_START (1 << 7)
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/* --- XAH_CTRL_0 (XAH_CTRL in 230) ---------------------------------------- */
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#define MAX_FRAME_RETRIES_SHIFT 4
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#define MAX_FRAME_RETRIES_MASK 0x0f
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#define MAX_CSMA_RETRIES_SHIFT 1
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#define MAX_CSMA_RETRIES_MASK 0x07
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#define SLOTTED_OPERATION (1 << 0) /* 231 only */
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/* --- CSMA_SEED_1 --------------------------------------------------------- */
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#define MIN_BE_SHIFT_230 6 /* 230 location */
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#define MIN_BE_MASK_230 3
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#define AACK_FVN_MODE_SHIFT 6 /* 231 only */
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#define AACK_FVN_MODE_MASK 3
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enum {
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AACK_FVN_MODE_0 = 0,
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AACK_FVN_MODE_01 = 1, /* reset default */
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AACK_FVN_MODE_012 = 2,
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AACK_FVN_MODE_ANY = 3
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};
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#define AACK_SET_PD (1 << 5)
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#define AACK_DIS_ACK (1 << 4) /* 231 only */
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#define I_AM_COORD (1 << 3)
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#define CSMA_SEED_1_SHIFT 0
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#define CSMA_SEED_1_MASK 7
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/* --- CSMA_BE ------------------------------------------------------------- */
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#define MAX_BE_SHIFT 4
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#define MAX_BE_MASK 0x0f
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#define MIN_BE_SHIFT 0 /* 231 location */
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#define MIN_BE_MASK 0x0f
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/* --- REG_CONT_TX_0 ------------------------------------------------------- */
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#define CONT_TX_MAGIC 0x0f
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/* --- REG_CONT_TX_1 (230 only) -------------------------------------------- */
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#define CONT_TX_MOD 0x00 /* modulated */
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#define CONT_TX_M2M 0x10 /* f_CH-2 MHz */
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#define CONT_TX_M500K 0x80 /* f_CH-0.5 MHz */
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#define CONT_TX_P500K 0xc0 /* f_CH+0.5 MHz */
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#endif /* !AT86RF230_H */
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