mirror of
git://projects.qi-hardware.com/ben-wpan.git
synced 2024-09-12 23:19:17 +03:00
- Makefile (DIRS): added atrf-xtal - atrf-xtal/Makefile: build atrf-xtal for the Ben or do nothing elsewhere - atrf-xtal/atrf-xtal.h, atrf-xtal/atrf-xtal.c: diagnostic utility to determine the transceiver's crystal frequency - atrf-xtal/atben.c: dirty low-level driver for ATBEN
143 lines
3.1 KiB
C
143 lines
3.1 KiB
C
/*
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* atrf-xtal/atben.c - ATBEN-specific low-level driver
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*
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* Written 2011 by Werner Almesberger
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* Copyright 2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/*
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* WARNING: this program does very nasty things to the Ben and it doesn't
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* like company. In particular, it resents:
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*
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* - the MMC driver - disable it with
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* echo jz4740-mmc.0 >/sys/bus/platform/drivers/jz4740-mmc/unbind
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* - the AT86RF230/1 kernel driver - use a kernel that doesn't have it
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* - anything that accesses the screen - kill GUI, X server, etc.
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* - the screen blanker - either disable it or make sure the screen stays
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* dark, e.g., with
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* echo 1 >/sys/devices/platform/jz4740-fb/graphics/fb0/blank
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* - probably a fair number of other daemons and things as well - best to
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* kill them all.
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*/
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/mman.h>
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#include "at86rf230.h"
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#include "atrf.h"
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#include "atrf-xtal.h"
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#define MAX_COUNT (1000*1000)
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static volatile void *base;
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static volatile uint32_t *clkgr;
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static uint32_t old_clkgr;
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void atben_setup(struct atrf_dsc *dsc, int size, int trim)
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{
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static uint8_t buf[127];
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atrf_reset_rf(dsc);
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_TRX_OFF);
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atrf_reg_write(dsc, REG_XOSC_CTRL,
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(XTAL_MODE_INT << XTAL_MODE_SHIFT) | trim);
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/* minimum TX power, maximize delays, disable CRC */
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switch (atrf_identify(dsc)) {
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case artf_at86rf230:
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atrf_reg_write(dsc, REG_PHY_TX_PWR, 0xf);
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break;
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case artf_at86rf231:
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atrf_reg_write(dsc, REG_PHY_TX_PWR, 0xff);
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atrf_reg_write(dsc, REG_TRX_CTRL_1, 0);
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break;
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default:
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abort();
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}
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atrf_reg_write(dsc, REG_TRX_STATE, TRX_CMD_PLL_ON);
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usleep(200); /* nominally 180 us worst-case */
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atrf_buf_write(dsc, buf, size);
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//atrf_reg_write(dsc, REG_IRQ_MASK, IRQ_TRX_END);
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atrf_reg_write(dsc, REG_IRQ_MASK, 0xff);
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mlockall(MCL_CURRENT);
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struct atrf_dsc {
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void *driver;
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void *handle;
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int chip_id;
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};
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struct atben_dsc {
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int fd;
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void *mem;
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};
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base = ((struct atben_dsc *) ((struct atrf_dsc *) dsc)->handle)->mem;
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clkgr = base+0x20;
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old_clkgr = *clkgr;
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*clkgr = old_clkgr | 1 << 10;
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}
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unsigned atben_sample(struct atrf_dsc *dsc)
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{
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unsigned i = MAX_COUNT;
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(void) atrf_reg_read(dsc, REG_IRQ_STATUS);
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#if 0
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while (i) {
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if (atrf_interrupt(dsc))
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break;
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i--;
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}
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#else
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volatile uint32_t *pdpin = base+0x10300;
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volatile uint32_t *pddats = base+0x10314;
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volatile uint32_t *pddatc = base+0x10318;
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volatile uint32_t *icmr = base+0x1004;
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volatile uint32_t *icmsr = base+0x1008;
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volatile uint32_t *icmcr = base+0x100c;
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#if 0
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atrf_slp_tr(dsc, 1);
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while (i) {
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if (*pdpin & 0x1000)
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break;
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i--;
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}
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atrf_slp_tr(dsc, 0);
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#endif
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uint32_t old_icmr = *icmr;
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*icmsr = 0xffffffff;
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*pddats = 1 << 9;
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*pddatc = 1 << 9;
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do i--;
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while (!(*pdpin & 0x1000));
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*icmcr = ~old_icmr;
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#endif
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return MAX_COUNT-i;
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}
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void atben_cleanup(struct atrf_dsc *dsc)
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{
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*clkgr = old_clkgr;
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}
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