mirror of
git://projects.qi-hardware.com/ben-wpan.git
synced 2024-11-25 21:18:26 +02:00
42483d67b4
At an interrupt barrier, the host must be able to ensure that no interrupt generated before reaching the barrier is still pending and will be delivered after crossing the barrier. For this, we introduce the following concept: - interrupts have a serial number. This number is sent to the host on EP 1 (currently bulk) to signal the interrupt, instead of the zero byte we used previously. - the new request ATUSB_SPI_WRITE2_SYNC returns the interrupt serial number from after the register write (the register write itself is the interrupt barrier). - the host can now check if the serial indicated from bulk and the serial from ATUSB_SPI_WRITE2_SYNC are the same. If yes, interrupts are synchronized. If not, it has to wait for the interrupt to be signaled on EP 1. We should also consider the case that the interrupt serial has gotten ahead of ATUSB_SPI_WRITE2_SYNC. But that seems to happen rarely. In any case, it's something for the host driver to worry about, not for the firmware. - board.h (irq_serial), board_app.c (irq_serial, INT0_vect): count the interrupt serial number and return it when signaling the interrupt - include/atusb/ep0.h (ATUSB_SPI_WRITE2_SYNC), ep0.c (my_setup): new request ATUSB_SPI_WRITE2_SYNC that does a register write, then returns the interrupt serial
97 lines
2.0 KiB
C
97 lines
2.0 KiB
C
/*
|
|
* fw/board.h - Board-specific functions and definitions
|
|
*
|
|
* Written 2008-2011 by Werner Almesberger
|
|
* Copyright 2008-2011 Werner Almesberger
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef BOARD_H
|
|
#define BOARD_H
|
|
|
|
#include <stdint.h>
|
|
|
|
|
|
#define LED_PORT B
|
|
#define LED_BIT 6
|
|
#define nRST_RF_PORT C
|
|
#define nRST_RF_BIT 7
|
|
#define SLP_TR_PORT B
|
|
#define SLP_TR_BIT 4
|
|
|
|
#define SCLK_PORT D
|
|
#define SCLK_BIT 5
|
|
#define MOSI_PORT D
|
|
#define MOSI_BIT 3
|
|
|
|
#define MISO_PORT D
|
|
#define MISO_BIT 2
|
|
#define nSS_PORT D
|
|
#define nSS_BIT 1
|
|
#define IRQ_RF_PORT D
|
|
#define IRQ_RF_BIT 0
|
|
|
|
|
|
#define SET_2(p, b) PORT##p |= 1 << (b)
|
|
#define CLR_2(p, b) PORT##p &= ~(1 << (b))
|
|
#define IN_2(p, b) DDR##p &= ~(1 << (b))
|
|
#define OUT_2(p, b) DDR##p |= 1 << (b)
|
|
#define PIN_2(p, b) ((PIN##p >> (b)) & 1)
|
|
|
|
#define SET_1(p, b) SET_2(p, b)
|
|
#define CLR_1(p, b) CLR_2(p, b)
|
|
#define IN_1(p, b) IN_2(p, b)
|
|
#define OUT_1(p, b) OUT_2(p, b)
|
|
#define PIN_1(p, b) PIN_2(p, b)
|
|
|
|
#define SET(n) SET_1(n##_PORT, n##_BIT)
|
|
#define CLR(n) CLR_1(n##_PORT, n##_BIT)
|
|
#define IN(n) IN_1(n##_PORT, n##_BIT)
|
|
#define OUT(n) OUT_1(n##_PORT, n##_BIT)
|
|
#define PIN(n) PIN_1(n##_PORT, n##_BIT)
|
|
|
|
|
|
#define USB_VENDOR 0x20b7 /* Qi Hardware */
|
|
#define USB_PRODUCT 0x1540 /* ben-wpan atusb */
|
|
|
|
#define DFU_USB_VENDOR USB_VENDOR
|
|
#define DFU_USB_PRODUCT USB_PRODUCT
|
|
|
|
|
|
#define BOARD_MAX_mA 40
|
|
|
|
#ifdef BOOT_LOADER
|
|
#define NUM_EPS 1
|
|
#else
|
|
#define NUM_EPS 2
|
|
#endif
|
|
|
|
#define HAS_BOARD_SERNUM
|
|
|
|
extern uint8_t board_sernum[42];
|
|
extern uint8_t irq_serial;
|
|
|
|
|
|
void reset_rf(void);
|
|
void reset_cpu(void);
|
|
uint8_t read_irq(void);
|
|
void slp_tr(void);
|
|
|
|
void led(int on);
|
|
void panic(void);
|
|
|
|
uint64_t timer_read(void);
|
|
void timer_init(void);
|
|
|
|
int gpio(uint8_t port, uint8_t data, uint8_t dir, uint8_t mask, uint8_t *res);
|
|
void gpio_cleanup(void);
|
|
|
|
void board_init(void);
|
|
void board_app_init(void);
|
|
|
|
#endif /* !BOARD_H */
|