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ben-wpan/atusd/ERRATA
Werner Almesberger 86e556ce92 First part of the board bringup: power and clock.
- atusd/ERRATA: variations of the circuit being debugged from the design
- tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable
  the board and (in the future) establish communication
- atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative
  load from scope probe
2010-09-04 23:14:57 -03:00

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- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
a bad trace. According to simulations, 22 pF should be more than enough.
- added wire connecting uSD-side ground plane to ground plane at outer edge,
to improve CLK signal return. (Probably unnecessary, too.)