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mirror of git://projects.qi-hardware.com/ben-wpan.git synced 2024-12-23 20:29:54 +02:00
ben-wpan/cntr/cntr.pro
Werner Almesberger 81ab679fbd The parasitic capacitance of the three probe input pins and R1 formed a
quite formidable low-pass filter that almost completely eliminated the
1 MHz signal.

- cntr/cntr.sch, cntr/cntr.brd: changed R1 from 100k to 1k to increase
  input bandwidth
2010-08-25 06:36:02 -03:00

73 lines
978 B
INI

update=Wed Aug 25 06:34:30 2010
last_client=pcbnew
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
SimCmd=
UseNetN=0
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=conn
LibName4=../components/c8051f320
LibName5=../components/mini_usb_b
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=320
PadDimH=600
PadDimV=600
BoardThickness=630
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
LastNetListRead=cntr.net
[pcbnew/libraries]
LibDir=
LibName1=../modules/mini-usb
LibName2=../modules/pads
LibName3=../modules/qfp
LibName4=../modules/stdpass