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41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
Version 20100903:
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- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
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a bad trace. According to simulations, 22 pF should be more than enough.
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- added wire connecting uSD-side ground plane to ground plane at outer edge,
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to improve CLK signal return. (Probably unnecessary, too.)
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- the footprint of the transistor (Q1) is reversed :-( It works after
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converting the chip from SOT to PLCC.
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- not an erratum, but with experiments showing power-on reset to be
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reliable, we can consider removing the hardware reset circuit. This will
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also simplify the layout.
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Version 20100908:
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- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
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this.
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- work-around on second 20100908 board: replace the resistive divider with
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a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:
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C7 -> 0 R
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R3 -> 33 pF
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R4 -> 220 pF
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Applied work-around also to first 20100908 board after confirming dismal
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performance caused by clock instability.
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- considering that the clock input has a Vpp of only 400-500 mV, we should
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have a ground plane also under as much of the the clock circuit as
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possible.
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- via between pins 1 and 32 is too close to the chip for DIY PCBs
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Version 20100912:
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- zone fill did not reach upper GND end of antenna. This was not intended,
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but may be harmless or even an improvement.
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