mirror of
git://projects.qi-hardware.com/ben-wpan.git
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ec21e4ba47
- ep0.c: the ATUSB EP0 protocol engine - Makefile (OBJS): added ep0.o - atusb.c (main): initialize the EP0 protocol - spi.h: whitespace cleanup usb/patches/support-vendor-requests.patch: - usb/ctrl.c (ctrl_handler): also pass vendor-specific requests to the class handler - class/CDC/cdc.c (cdc_req_handler): reject vendor requests
78 lines
1.3 KiB
C
78 lines
1.3 KiB
C
#include <stdint.h>
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#include <avr/io.h>
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#define F_CPU 8000000UL
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#include <util/delay.h>
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#include "freakusb.h"
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#include "at86rf230.h"
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#include "io.h"
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#include "spi.h"
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void reset_rf(void);
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void ep0_init(void);
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void reset_rf(void)
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{
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/* AT86RF231 data sheet, 12.4.13, reset pulse width: 625 ns (min) */
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CLR(nRST_RF);
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_delay_us(1);
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SET(nRST_RF);
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/* 12.4.14: SPI access latency after reset: 625 ns (min) */
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_delay_us(1);
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}
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int main(void)
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{
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/* We start with a 1 MHz/8 clock. Disable the prescaler. */
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CLKPR = 1 << CLKPCE;
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CLKPR = 0;
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/* set up all the outputs; default port value is 0 */
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OUT(LED);
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OUT(nRST_RF); /* resets the transceiver */
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OUT(SLP_TR);
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spi_init();
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reset_rf();
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/* switch CLKM to 8 MHz */
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/*
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* @@@ Note: Atmel advise against changing the external clock in
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* mid-flight. We should therefore switch to the RC clock first, then
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* crank up the external clock, and finally switch back to the external
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* clock. The clock switching procedure is described in the ATmega32U2
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* data sheet in secton 8.2.2.
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*/
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spi_begin();
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spi_send(AT86RF230_REG_WRITE | REG_TRX_CTRL_0);
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spi_send(CLKM_CTRL_8MHz);
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spi_end();
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/* now we should be at 8 MHz */
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SET(LED);
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_delay_ms(100);
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CLR(LED);
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usb_init();
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ep0_init();
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hw_init();
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while (1)
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usb_poll();
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}
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