mirror of
git://projects.qi-hardware.com/ben-wpan.git
synced 2024-12-29 10:09:54 +02:00
f17bcebce7
- atusb.brd: enabled Drawings layer - atusb.brd: moved board dimensions to Drawings layer - Makefile (clean): added $(NAME)-Drawings.gbr - Makefile (GMERGE, gerber): use "gmerge" to merge Comments (which now only contains the component references) into SilkS_Front - Makefile (gerbv): Comments is now redundant; removed it
110 lines
2.9 KiB
Makefile
110 lines
2.9 KiB
Makefile
PLOT_BRD = pcbnew --plot=ps_a4 --ps-pads-drill-opt=none --fill-all-zones
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CPTX = ../../eda-tools/mlztx/cptx
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GMERGE = ../../eda-tools/gerber/gmerge
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NAME = atusb
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VERSION = 110314
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DIR = $(NAME)
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.PHONY: all gen generate sch brd xpdf front back clean
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.PHONY: gerber gerbv fab
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all:
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@echo "make what ? target: gen sch brd xpdf front back clean"
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@exit 1
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gen generate:
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eeschema --plot=ps `pwd`/$(NAME).sch
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# need scripts
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sch:
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eeschema `pwd`/$(NAME).sch
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brd:
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pcbnew `pwd`/$(NAME).brd
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xpdf:
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xpdf $(NAME).pdf
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front: $(NAME)-Front.ps
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lpr $<
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back: $(NAME)-Back.ps
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lpr $<
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cptx:
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$(CPTX) -i $(NAME).brd 0 47000 48100 21 46811 40591
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# --- DIY production (toner transfer) -----------------------------------------
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#
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# Postscript for production of front/back layer, using the toner transfer
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# method. Note that other artwork transfer methods may require different
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# mirror settings.
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#
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# We use --ps-pads-drill-opt=none to avoid having any hole before drilling,
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# which yields the best results with a CNC drill. For manual drilling, "real"
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# would be preferrable. Do not use "small", for this created holes that are
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# larger (!) than designed.
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#
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%-Front.ps: %.brd
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$(PLOT_BRD) -l Front --mirror $<
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%-Back.ps: %.brd
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$(PLOT_BRD) -l Back $<
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# --- Industrial production ---------------------------------------------------
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PCB_FILES = README-PCB $(NAME)-PCB_Edges.dxf $(NAME).drl \
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$(NAME)-SilkS_Front.gto $(NAME)-Mask_Front.gts \
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$(NAME)-Front.gtl $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs \
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$(NAME)-PCB_Edges.gbr
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gerber:
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pcbnew --plot=gerber --origin=aux \
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-l `pcbnew --list-layers $(NAME).brd | tr '\012' ,` \
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--fill-all-zones $(NAME).brd \
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--exclude-pcb-edge
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$(GMERGE) $(NAME)-SilkS_Front.gto $(NAME)-Comments.gbr >_tmp \
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|| { rm -rf _tmp; exit 1; }
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mv _tmp $(NAME)-SilkS_Front.gto
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fab: gerber
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pcbnew --plot=dxf --origin=aux -l PCB_Edges $(NAME).brd
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pcbnew --drill --origin=aux $(NAME).brd
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mkdir -p fab
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tar Ccfz .. fab/$(NAME)-pcb-$(VERSION).tar.gz \
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$(PCB_FILES:%=$(DIR)/%)
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cd ..; zip -l $(DIR)/fab/$(NAME)-pcb-$(VERSION).zip \
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$(PCB_FILES:%=$(DIR)/%)
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gerbv:
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gerbv $(NAME)-SilkS_Front.gto \
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$(NAME)-SoldP_Front.gtp \
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$(NAME)-Front.gtl \
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$(NAME)-Mask_Front.gts \
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$(NAME)-Back.gbl
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upload:
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qippl fab/$(NAME)-pcb-$(VERSION).tar.gz \
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fab/$(NAME)-pcb-$(VERSION).zip wpan/fab
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# --- Cleanup -----------------------------------------------------------------
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clean:
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rm -f $(NAME)-Front.ps $(NAME)-Back.ps
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rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr $(NAME)-PCB_Edges.dxf
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rm -f $(NAME)-Front.gtl $(NAME)-Mask_Front.gts
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rm -f $(NAME)-SilkS_Front.gto $(NAME)-SoldP_Front.gtp
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rm -f $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs
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rm -f $(NAME)-SilkS_Back.gbo $(NAME)-SoldP_Back.gbp
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rm -f $(NAME)-Comments.gbr $(NAME)-Drawings.gbr
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spotless: clean
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rm -f '$$'savepcb.brd
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rm -f $(NAME)-cache.bak atrf.bak usb.bak
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rm -f $(NAME).000
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rm -f $(NAME).net
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