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84 lines
5.6 KiB
Plaintext
84 lines
5.6 KiB
Plaintext
1, CON3 , I saw the pcb file , it has total 8 pins, must be only 3 pins and ground. do you want to use MS24011P3R(1.0mm pitch right angle smaller one) or MS24013R(1.25mm pitch right angle)
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if we need use MS24011P3R, please see the http://downloads.qi-hardware.com/hardware/qi_avt2/v1.0/datasheet/CON3~MS24011P3R~~FINAL_PART~~.pdf
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please ignore I sent you the sample MS24011P3RA, it's wrong sample(180 degree). I'll request for the real one (MS24011P3R).
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[OK]{2}, I found that good you use always thermal pad (we called for cross solder paste), it's good for solder manually (MP stage), but you need be
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careful, Like U2 pin4 has thick trace but pin3 (L1.1)doesn't have the same width, it's not good. Current in needed be equal to keep current out based on width common ground.
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same story on U3.3 <-> L2.1, please see http://downloads.qi-hardware.com/hardware/qi_avt2/v1.0/datasheet/U2_3~EUP3406.pdf
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page 10.
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[OK]{3}, N-000077 & N-000065 should be the same width as N-000065 & N-00068, others are not mentioned here i think should be modified like this.
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Main audio signal path should all keep the same width; but control signal like any MOSFET's Gate doesn't need. [1]
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[OK]{4}, J3 on avt2_RC1 I made a mistake on placement, did you find? It should be shift to left a little bit to meet mechanical as well.
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please see [2].
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[OK]{5}, I very agree and like you out U1.187 pin to be the bigger ground area, I should do like yours to expand copper; but one thing
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please must be changed back a little bit, becuase I ask Ingenic and cob vendor, the ground copper under cpu die should be
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add a little bit width than itself, for example , the jz4720 the die size is 4560um * 4960um, so they normally make a baseplate expandly
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to 5160um * 4760um by added plus 200um for each. Surrounding this area i think you still can use thermal copper pad.
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6, I found you used 0.099mm(~3.89mil) width for each expanding bonding wire, it's differ from my 0.125mm(~4.92mil), I know now
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have many pcb maker they have accurate process can do above 3 mil trace butthey just officially anouncement they can do it on some sample or small run,
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but for MP, their quality will hardly to maintain the same width with constant variance in every lot; maybe I produced some Moto phone in china before
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, but we still meet a lot of defective rate or WIP in MP due to pcba maker's process; I am not sure how many lot of pcb your company made; if running a small quantity,
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they just picked the best one lot and send to you. But I have met many kind of this huge for MOTO project before, even the pcb maker they
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anoucement they can control the quality.
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so I used to choose a safe width around 5 mil for trace, also I arranged a 0.15mm(5.9mil)/0.12mm(4.7mil)/0.15mm(5.9mil) for sectorial shape in:
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pcb layout plan:
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--> approximately --> 6 mil width pad / 5 mil width gap / 6 mil width pad and so on...
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after pcb maker's etching process, they will become variably as:
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--> approximately --> 5 / 6 / 5
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so this 5mil pad will be coonected to all thin control signal trace ( smaller than 4.9 mil )
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now yours is :
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--> approximately --> 4.92 mil width pad / 3.38 mil width gap / 4.92 mil width pad
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after pcb maker's etching process, they will become variably as:
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--> approximately --> 3.9 / 4.3 / 3.9
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so this 3.9mil pad will be connected to all thin control signal trace ( smaller than 3.89 mil )
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why I designed like this:
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a) the width of golden wire is 0.7mil here in Taiwan cob vendor but China has 0.8mil aluminum capability.
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so the most safe space is more bigger than 2 times of 0.8mil = 1.6 mil (40.65um) which is a bit smaller than die pad only.
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see the smallest pad on cpu die is 50*50um only[3], so chose 0.7 mil is more safe and aslo i can only find here Taipei they
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have; but for design a reference board , maybe in the future, some one will use our design and make A LOT quantity hopefully
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but China's COB we're now still hard to find a suitable for our few scale.
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b) the example small distance between CPU pad 73 and 74 is 76um only, so the explosion sectorially from cpu die to bonding outside pad, should be
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carefull.
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c) the Ben- NanoNote our OEM they don't use all 186 pins of jz4720, so they only layout for 165 pins bonding wires for the cob pad as a square shape.
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d) at SilkS_Cmp layer for cpu die, please mark two cross which needed to position for cob vendor they write program to make position.
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[4] ??
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7, you cancelled XP/XN, YP/YN? touch screen? I left them becuase of someone is crazy he wants to study touch screen future.
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I think you have good reason, right?
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[OK]{8}, R39= 2.2K/5%, sorry the schematic is 22k, please change schematic to 2.2K/5%, avt2_RC1 is 2.2K/5%.
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¿9?, R40 & R41 is 100/5% in schematic but I found I make mistakes again, in avt2_RC1 I used 1k/5%, but it still works well due
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to volatage divided, so bom I changed it correct into 100/5% now.
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[OK]{10}, R60 100K/5% R0603 must move to somewhere, otherwise the batttery case will interfere it. If you agree, we can change this package 0603 into 0402.
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[OK]{11}, SW1 not changed to P/N: MK-12C02-PB, see [5]
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[5] http://downloads.qi-hardware.com/hardware/qi_avt2/v1.0/datasheet/SW1~MK-12C02-PB.pdf
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[OK]{12}, C59, C62 is 100uF/4V in qi_lb60 (Ben-Nanonote) they used A-case in huge quantity, here I can not get, so I changed to
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100uF/6.3V B-case.
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13, C72, C73 are C0805, I am requesting the parts. ¿?
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14, I cann't figure out the footprint of key [6],
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[OK]{15}, shift uSD a little bit
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[OK]{16}, add 0.1uF/16V /C0402 between U6 pin1 and pin2 ¿?
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