2010-09-02 00:27:14 +03:00
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#pypp 0
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// Iris: micro-kernel for a capability-based operating system.
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// source/usb-mass-storage.ccp: USB mass storage device driver.
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// Copyright 2009-2010 Bas Wijnen <wijnen@debian.org>
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include "iris.hh"
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#include "devices.hh"
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#define ARCH
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#include "arch.hh"
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#if 0
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States and expected interrupts:
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IDLE: after reset or csw.
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IN interrupt: csw received, do nothing.
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OUT interrupt: cbw; handle
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-> IDLE (no data; csw sent)
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-> CSW (data sent in one packet)
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-> TX (more than one packet to send)
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-> RX (receive packets)
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TX: transmitting data.
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IN interrupt: host received data; send more.
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-> TX (more to send)
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-> CSW (last data has now been sent)
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RX: receiving data.
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OUT interrupt: host sent data; handle.
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-> RX (more to receive)
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-> IDLE (done receiving; send csw)
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CSW: waiting to transmit csw.
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IN interrupt: TX is done; send csw
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-> IDLE
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#endif
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extern "C":
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void *memset (char *s, int c, unsigned long n):
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Iris::debug ("memset called: %x %x->%x\n", s, n, c)
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for unsigned i = 0; i < n; ++i:
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s[i] = c
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return s
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class Udc:
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typedef unsigned char u8
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typedef unsigned short u16
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typedef unsigned int u32
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typedef u8 string
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// The ugly stuff is because pypp doesn't support __attribute__.
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/**/struct Setup {
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u8 request_type;
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u8 request;
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u16 value;
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u16 index;
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u16 length;
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} __attribute__ ((packed))
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/**/struct Device {
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static u8 const Type = 1;
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u8 length;
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u8 type;
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u16 usb_version;
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u8 dev_class;
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u8 subclass;
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u8 protocol;
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u8 max_packet_size0;
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u16 vendor;
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u16 product;
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u16 dev_version;
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string s_manufacturer;
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string s_product;
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string s_serial;
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u8 num_configurations;
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} __attribute__ ((packed))
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/**/struct Configuration {
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static u8 const Type = 2;
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u8 length;
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u8 type;
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u16 total_length;
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u8 num_interfaces;
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u8 configuration_value;
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u8 configuration;
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u8 attributes;
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u8 max_power;
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} __attribute__ ((packed))
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/**/struct Interface {
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static u8 const Type = 4;
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u8 length;
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u8 type;
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u8 interface;
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u8 alternate;
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u8 num_endpoints;
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u8 iface_class;
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u8 subclass;
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u8 protocol;
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string name;
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} __attribute__ ((packed))
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/**/struct Endpoint {
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static u8 const Type = 5;
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u8 length;
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u8 type;
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u8 address;
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u8 attributes;
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u16 max_packet_size;
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u8 interval;
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} __attribute__ ((packed))
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/**/struct Device_Qualifier {
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static u8 const Type = 6;
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u8 length;
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u8 type;
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u16 version;
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u8 dev_class;
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u8 subclass;
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u8 protocol;
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u8 max_packet_size0;
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u8 num_configurations;
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u8 reserved;
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} __attribute__ ((packed))
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/**/struct Langs {
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static u8 const Type = 3;
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u8 length;
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u8 type;
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u8 lang;
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} __attribute__ ((packed))
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template <unsigned size> struct String {
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static u8 const Type = 3;
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u8 length;
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u8 type;
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u16 data[size];
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} __attribute__ ((packed))
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/**/struct CBW {
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u32 sig;
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u32 tag;
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u32 length;
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u8 flags;
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u8 lun;
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u8 size;
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u8 data[16];
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enum Code {
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TEST_UNIT_READY = 0x00,
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2010-09-09 22:48:35 +03:00
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REQUEST_SENSE = 0x03,
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FORMAT_UNIT = 0x04,
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INQUIRY = 0x12,
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RESERVE6 = 0x16,
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RELEASE6 = 0x17,
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SEND_DIAGNOSTIC = 0x1d,
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2010-09-02 00:27:14 +03:00
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READ_CAPACITY = 0x25,
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2010-09-09 22:48:35 +03:00
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READ10 = 0x28,
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WRITE10 = 0x2a,
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RESERVE10 = 0x56,
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RELEASE10 = 0x57
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2010-09-02 00:27:14 +03:00
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};
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} __attribute__ ((packed))
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static unsigned const max_packet_size0 = 64
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static unsigned const max_packet_size_bulk = 64
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enum Requests:
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GET_STATUS = 0
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CLEAR_FEATURE = 1
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SET_FEATURE = 3
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SET_ADDRESS = 5
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GET_DESCRIPTOR = 6
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SET_DESCRIPTOR = 7
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GET_CONFIGURATION = 8
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SET_CONFIGURATION = 9
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GET_INTERFACE = 10
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SET_INTERFACE = 11
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SYNCH_FRAME = 12
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enum Storage_requests:
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BULK_ONLY_RESET = 0xff
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GET_MAX_LUN = 0xfe
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enum Request_types:
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STANDARD_TO_DEVICE = 0
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CLASS_TO_DEVICE = 0x20
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VENDOR_TO_DEVICE = 0x40
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STANDARD_TO_INTERFACE = 1
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CLASS_TO_INTERFACE = 0x21
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VENDOR_TO_INTERFACE = 0x41
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STANDARD_TO_ENDPOINT = 2
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CLASS_TO_ENDPOINT = 0x22
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VENDOR_TO_ENDPOINT = 0x42
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STANDARD_FROM_DEVICE = 0x80
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CLASS_FROM_DEVICE = 0xa0
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VENDOR_FROM_DEVICE = 0xc0
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STANDARD_FROM_INTERFACE = 0x81
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CLASS_FROM_INTERFACE = 0xa1
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VENDOR_FROM_INTERFACE = 0xc1
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STANDARD_FROM_ENDPOINT = 0x82
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CLASS_FROM_ENDPOINT = 0xa2
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VENDOR_FROM_ENDPOINT = 0xc2
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enum Endpoint_types:
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CONTROL = 0
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ISOCHRONOUS = 1
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BULK = 2
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INTERRUPT = 3
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enum Endpoint_features:
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ENDPOINT_HALT = 0
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/**/struct my_config {
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Configuration config;
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Interface interface;
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Endpoint endpoint[2];
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} __attribute__ ((packed))
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static Device device_descriptor
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//static Device_Qualifier device_qualifier_descriptor
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static my_config config_descriptor; //, other_config_descriptor
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static String <1> s_langs
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static String <6> s_manufacturer
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static String <16> s_product
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static String <12> s_serial
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char configuration
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unsigned get_descriptor (unsigned type, unsigned idx, unsigned len)
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unsigned handle_setup (Setup *s)
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void irq_usb ()
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void irq_in0 ()
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void irq_out ()
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void send_csw ()
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unsigned big_endian (unsigned src)
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2010-09-08 19:08:57 +03:00
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bool handle_interrupt (bool usb, bool in)
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void stall (unsigned error)
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bool stalling[3]
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2010-09-02 00:27:14 +03:00
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unsigned residue
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unsigned status
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2010-09-08 19:08:57 +03:00
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unsigned tag
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2010-09-02 00:27:14 +03:00
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unsigned block_bits
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Iris::WBlock block
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2010-09-09 22:48:35 +03:00
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Iris::Page buffer_page
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// A random address to map the buffer.
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static unsigned const buffer = 0x15000
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2010-09-02 00:27:14 +03:00
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public:
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void init (Iris::WBlock b)
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void log (unsigned c)
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void interrupt ()
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2010-09-08 19:08:57 +03:00
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void send (unsigned ep, char const *data, unsigned length, unsigned maxlength)
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void send_padded (char const *data, unsigned length, unsigned maxlength)
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2010-09-02 00:27:14 +03:00
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Udc::Device Udc::device_descriptor
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Udc::my_config Udc::config_descriptor
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Udc::String <1> Udc::s_langs
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Udc::String <6> Udc::s_manufacturer
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Udc::String <16> Udc::s_product
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Udc::String <12> Udc::s_serial
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void Udc::init (Iris::WBlock b):
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block = b
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block_bits = block.get_align_bits ()
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2010-09-09 22:48:35 +03:00
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// Set up the buffer page.
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buffer_page = Iris::my_memory.create_page ()
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buffer_page.set_flags (Iris::Page::PAYING)
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Iris::my_memory.map (buffer_page, buffer)
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2010-09-02 00:27:14 +03:00
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// Initialize the globals. My method of compiling doesn't handle global constructors.
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device_descriptor = (Device){ sizeof (Device), Device::Type, 0x200, 0, 0, 0, max_packet_size0, 0xfffe, 0x0002, 0x100, 1, 2, 3, 1 }
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config_descriptor = (my_config){
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(Configuration){ sizeof (Configuration), Configuration::Type, sizeof (my_config), 1, 1, 0, 0xc0, 30 },
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(Interface){ sizeof (Interface), Interface::Type, 0, 0, 2, 0x8, 0x6, 0x50, 0 }, {
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(Endpoint){ sizeof (Endpoint), Endpoint::Type, 1, BULK, max_packet_size_bulk, 0 },
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(Endpoint){ sizeof (Endpoint), Endpoint::Type, 0x82, BULK, max_packet_size_bulk, 0 }
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}
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}
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s_langs = (String <1>){ sizeof (String <1>), String <1>::Type, { 0x0409 } }
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s_manufacturer = (String <6>){ sizeof (String <6>), String <6>::Type, { 's', 'h', 'e', 'v', 'e', 'k' } }
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s_product = (String <16>){ sizeof (String <16>), String <16>::Type, { 'I', 'r', 'i', 's', ' ', 'o', 'n', ' ', 'N', 'a', 'n', 'o', 'N', 'o', 't', 'e' } }
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s_serial = (String <12>){ sizeof (String <12>), String <12>::Type, { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B' } }
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cpm_start_udc ()
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// Disconnect from the bus and don't try to get high-speed.
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UDC_POWER = 0
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UDC_TESTMODE = 0
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configuration = 0
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2010-09-09 22:48:35 +03:00
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// Set max packet sizes.
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UDC_INDEX = 1
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UDC_OUTMAXP = max_packet_size_bulk
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UDC_OUTCSR = UDC_OUTCSR_CDT | UDC_OUTCSR_FF
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UDC_OUTCSR = UDC_OUTCSR_CDT | UDC_OUTCSR_FF
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UDC_INDEX = 2
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UDC_INMAXP = max_packet_size_bulk
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UDC_INCSRH = UDC_INCSRH_MODE
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UDC_INCSR = UDC_INCSR_CDT | UDC_INCSR_FF
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UDC_INCSR = UDC_INCSR_CDT | UDC_INCSR_FF
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2010-09-02 00:27:14 +03:00
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// exit suspend mode by reading the interrupt register.
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unsigned i = UDC_INTRUSB
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// reset all pending endpoint interrupts.
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i = UDC_INTRIN
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i = UDC_INTROUT
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// enable interrupt on bus reset.
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UDC_INTRUSBE = UDC_INTR_RESET
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2010-09-09 22:48:35 +03:00
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// enable interrupts on endpoint 0 and in endpoint 2
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UDC_INTRINE = 1 << 0 | 1 << 2
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// and on out endpoint 1.
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UDC_INTROUTE = 1 << 1
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2010-09-02 00:27:14 +03:00
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// Wait a while.
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Iris::sleep (HZ / 10)
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// Connect to the host.
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UDC_POWER = UDC_POWER_SOFTCONN
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// Initialize cbw state
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status = 0
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residue = 0
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2010-09-08 19:08:57 +03:00
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void Udc::send (unsigned ep, char const *data, unsigned length, unsigned maxlength):
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2010-09-02 00:27:14 +03:00
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if maxlength < length:
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length = maxlength
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unsigned i
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for i = 0; (length - i & ~3) > 0 && i < length; i += 4:
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UDC_FIFO (ep) = ((unsigned *)data)[i / 4]
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2010-09-09 22:48:35 +03:00
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//kdebug_num (((unsigned *)data)[i / 4], 8)
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//kdebug (" ")
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2010-09-02 00:27:14 +03:00
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for ; i < length; ++i:
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UDC_FIFO8 (ep) = data[i]
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2010-09-09 22:48:35 +03:00
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//kdebug_num (data[i], 2)
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//kdebug (" ")
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2010-09-02 00:27:14 +03:00
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2010-09-08 19:08:57 +03:00
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void Udc::send_padded (char const *data, unsigned length, unsigned maxlength):
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2010-09-09 22:48:35 +03:00
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UDC_INDEX = 2
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if UDC_INCSR & UDC_INCSR_INPKTRDY:
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Iris::panic (0, "sending padded not possible because a packet is already waiting.\n")
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2010-09-02 00:27:14 +03:00
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unsigned len = length < maxlength ? length : maxlength
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residue = maxlength - len
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len = (len + 3) & ~3
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2010-09-08 19:08:57 +03:00
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send (2, data, len, maxlength)
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2010-09-02 00:27:14 +03:00
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while len + 3 < maxlength:
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2010-09-08 19:08:57 +03:00
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UDC_FIFO (2) = 0
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2010-09-02 00:27:14 +03:00
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len += 4
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2010-09-09 22:48:35 +03:00
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//kdebug_char ('-')
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2010-09-02 00:27:14 +03:00
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while len < maxlength:
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2010-09-08 19:08:57 +03:00
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UDC_FIFO8 (2) = 0
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2010-09-02 00:27:14 +03:00
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++len
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2010-09-09 22:48:35 +03:00
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//kdebug_char ('.')
|
2010-09-08 19:08:57 +03:00
|
|
|
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
|
|
|
while true:
|
|
|
|
Iris::register_interrupt (IRQ_UDC)
|
|
|
|
Iris::wait_for_interrupt (IRQ_UDC)
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("interrupt pad\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
unsigned usb = UDC_INTRUSB
|
|
|
|
unsigned in = UDC_INTRIN
|
|
|
|
unsigned out = UDC_INTROUT
|
|
|
|
if usb & 4 || in & 1:
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("general interrupt pad\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
if !handle_interrupt (usb & 4, in & 1):
|
|
|
|
return
|
|
|
|
if out & 2:
|
|
|
|
Iris::panic (0, "out interrupt while waiting for in")
|
|
|
|
if in & 4:
|
|
|
|
break
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("done interrupt pad\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
|
|
|
|
unsigned Udc::get_descriptor (unsigned type, unsigned idx, unsigned len):
|
|
|
|
switch type:
|
|
|
|
case Configuration::Type:
|
|
|
|
if idx != 0:
|
|
|
|
return false
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get config descriptor\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, reinterpret_cast <char const *> (&config_descriptor), sizeof (config_descriptor), len)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case Device::Type:
|
|
|
|
if idx != 0:
|
|
|
|
return false
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get device descriptor\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, reinterpret_cast <char const *> (&device_descriptor), sizeof (device_descriptor), len)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case Device_Qualifier::Type:
|
|
|
|
//if idx != 0:
|
|
|
|
// return false
|
2010-09-08 19:08:57 +03:00
|
|
|
//send (0, reinterpret_cast <char const *> (&device_qualifier_descriptor), sizeof (device_qualifier_descriptor), len)
|
|
|
|
//return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
//break
|
|
|
|
return ~0
|
|
|
|
// The 6 is an arbitrary number, except that String <6> is instantiated already.
|
|
|
|
case String <6>::Type:
|
|
|
|
switch idx:
|
|
|
|
case 0:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get language descriptor\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, reinterpret_cast <char const *> (&s_langs), sizeof (s_langs), len)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case 1:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get manufacturer descriptor\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, reinterpret_cast <char const *> (&s_manufacturer), sizeof (s_manufacturer), len)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case 2:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get product descriptor\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, reinterpret_cast <char const *> (&s_product), sizeof (s_product), len)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case 3:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get serial descriptor\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, reinterpret_cast <char const *> (&s_serial), sizeof (s_serial), len)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
|
|
|
|
unsigned Udc::handle_setup (Setup *s):
|
|
|
|
switch s->request_type:
|
|
|
|
case STANDARD_TO_DEVICE:
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INDEX = 0
|
|
|
|
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
2010-09-02 00:27:14 +03:00
|
|
|
switch s->request:
|
|
|
|
case SET_ADDRESS:
|
|
|
|
UDC_FADDR = s->value
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("set address %x\n", s->value)
|
2010-09-02 00:27:14 +03:00
|
|
|
return 0
|
|
|
|
case SET_CONFIGURATION:
|
|
|
|
if s->value >= 2:
|
|
|
|
return ~0
|
|
|
|
configuration = s->value
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("set configuration %x\n", s->value)
|
2010-09-02 00:27:14 +03:00
|
|
|
return 0
|
|
|
|
case SET_INTERFACE:
|
|
|
|
if s->value != 0:
|
|
|
|
return ~0
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("set interface %x\n", s->value)
|
2010-09-02 00:27:14 +03:00
|
|
|
return 0
|
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
case STANDARD_FROM_DEVICE:
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INDEX = 0
|
|
|
|
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
2010-09-02 00:27:14 +03:00
|
|
|
switch s->request:
|
|
|
|
case GET_STATUS:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get status\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, "\0\0", 2, s->length)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case GET_DESCRIPTOR:
|
|
|
|
return get_descriptor ((s->value >> 8) & 0xff, s->value & 0xff, s->length)
|
|
|
|
case GET_CONFIGURATION:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get configuration\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, &configuration, 1, s->length)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
case GET_INTERFACE:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get interface\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, "\0", 1, s->length)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
case STANDARD_TO_ENDPOINT:
|
|
|
|
switch s->request:
|
|
|
|
case CLEAR_FEATURE:
|
|
|
|
switch s->value:
|
|
|
|
case ENDPOINT_HALT:
|
|
|
|
switch s->index:
|
|
|
|
case 0x82:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("in ep halt reset\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_INDEX = 2
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INCSR &= ~UDC_INCSR_SENDSTALL
|
2010-09-08 19:08:57 +03:00
|
|
|
stalling[2] = false
|
2010-09-09 22:48:35 +03:00
|
|
|
break
|
2010-09-02 00:27:14 +03:00
|
|
|
case 1:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("out ep halt reset\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_INDEX = 1
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_OUTCSR &= ~UDC_OUTCSR_SENDSTALL
|
2010-09-08 19:08:57 +03:00
|
|
|
stalling[1] = false
|
2010-09-09 22:48:35 +03:00
|
|
|
break
|
2010-09-02 00:27:14 +03:00
|
|
|
default:
|
|
|
|
return ~0
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INDEX = 0
|
|
|
|
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
|
|
|
return 0
|
2010-09-02 00:27:14 +03:00
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
case CLASS_FROM_INTERFACE:
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INDEX = 0
|
|
|
|
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
2010-09-02 00:27:14 +03:00
|
|
|
switch s->request:
|
|
|
|
case GET_MAX_LUN:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("get max lun\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
send (0, "\0", 1, s->length)
|
|
|
|
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
2010-09-02 00:27:14 +03:00
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
case CLASS_TO_INTERFACE:
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INDEX = 0
|
|
|
|
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
2010-09-02 00:27:14 +03:00
|
|
|
switch s->request:
|
|
|
|
case BULK_ONLY_RESET:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("bulk reset\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
return 0
|
|
|
|
default:
|
|
|
|
return ~0
|
|
|
|
default:
|
|
|
|
Iris::debug ("request: %x %x %x %x %x\n", s->request_type, s->request, s->index, s->length, s->value)
|
|
|
|
return ~0
|
|
|
|
|
|
|
|
void Udc::irq_usb ():
|
|
|
|
// Reset.
|
|
|
|
// enable interrupts on endpoint 0 and in endpoint 2
|
|
|
|
UDC_INTRINE = 1 << 0 | 1 << 2
|
|
|
|
// and on out endpoint 1.
|
|
|
|
UDC_INTROUTE = 1 << 1
|
|
|
|
UDC_INDEX = 1
|
|
|
|
// Do this twice to flush a double-buffered fifo completely.
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_OUTMAXP = max_packet_size_bulk
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
|
|
|
UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
|
|
|
UDC_INDEX = 2
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_INMAXP = max_packet_size_bulk
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_INCSR |= UDC_INCSR_CDT
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("usb reset\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
|
|
|
|
void Udc::irq_in0 ():
|
|
|
|
// Interrupt on endpoint 0.
|
2010-09-08 19:08:57 +03:00
|
|
|
UDC_INDEX = 0
|
2010-09-02 00:27:14 +03:00
|
|
|
unsigned csr = UDC_CSR0
|
|
|
|
if csr & UDC_CSR0_SENTSTALL:
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_CSR0 = 0
|
|
|
|
//Iris::debug ("stall done\t")
|
2010-09-02 00:27:14 +03:00
|
|
|
if csr & UDC_CSR0_SETUPEND:
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_CSR0 = UDC_CSR0_SVDSETUPEND
|
|
|
|
//Iris::debug ("setup aborted\t")
|
2010-09-02 00:27:14 +03:00
|
|
|
if !(csr & UDC_CSR0_OUTPKTRDY):
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("no packet 0: %x\n", csr)
|
2010-09-02 00:27:14 +03:00
|
|
|
return
|
|
|
|
union { unsigned d[2]; Setup s; } packet
|
|
|
|
packet.d[0] = UDC_FIFO (0)
|
|
|
|
packet.d[1] = UDC_FIFO (0)
|
|
|
|
if !(packet.s.request_type & 0x80) && packet.s.length > 0:
|
|
|
|
// More data will follow; unsupported.
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("packet on ep0 too long\n")
|
|
|
|
UDC_CSR0 = UDC_CSR0_SENDSTALL
|
2010-09-02 00:27:14 +03:00
|
|
|
return
|
|
|
|
UDC_INDEX = 1
|
|
|
|
UDC_OUTCSR |= UDC_OUTCSR_CDT
|
|
|
|
UDC_INDEX = 2
|
|
|
|
UDC_INCSR |= UDC_INCSR_CDT
|
2010-09-09 22:48:35 +03:00
|
|
|
unsigned ret = handle_setup (&packet.s)
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_INDEX = 0
|
|
|
|
if ret == ~0:
|
|
|
|
Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value)
|
2010-09-09 22:48:35 +03:00
|
|
|
UDC_CSR0 = UDC_CSR0_SENDSTALL
|
2010-09-02 00:27:14 +03:00
|
|
|
return
|
2010-09-09 22:48:35 +03:00
|
|
|
if ret:
|
|
|
|
UDC_CSR0 = ret
|
|
|
|
//kdebug ("done in0\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
|
|
|
|
void Udc::send_csw ():
|
|
|
|
UDC_INDEX = 2
|
|
|
|
UDC_FIFO (2) = 0x53425355
|
2010-09-08 19:08:57 +03:00
|
|
|
UDC_FIFO (2) = tag
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_FIFO (2) = residue
|
|
|
|
UDC_FIFO8 (2) = status
|
|
|
|
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
|
|
|
status = 0
|
|
|
|
residue = 0
|
2010-09-08 19:08:57 +03:00
|
|
|
while true:
|
|
|
|
Iris::register_interrupt (IRQ_UDC)
|
|
|
|
Iris::wait_for_interrupt (IRQ_UDC)
|
|
|
|
unsigned usb = UDC_INTRUSB
|
|
|
|
unsigned in = UDC_INTRIN
|
|
|
|
if usb & 4 || in & 1:
|
|
|
|
if !handle_interrupt (usb & 4, in & 1):
|
|
|
|
return
|
|
|
|
if in & 4:
|
|
|
|
break
|
|
|
|
unsigned out = UDC_INTROUT
|
|
|
|
if out & 2:
|
|
|
|
Iris::panic (0, "out interrupt while waiting for in after csw")
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("sent csw\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
|
|
|
|
void Udc::stall (unsigned error):
|
|
|
|
unsigned index = UDC_INDEX
|
2010-09-09 22:48:35 +03:00
|
|
|
if stalling[index]:
|
|
|
|
Iris::debug ("already stalling!\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
if index == 1:
|
|
|
|
UDC_OUTCSR |= UDC_OUTCSR_SENDSTALL
|
|
|
|
else:
|
|
|
|
UDC_INCSR |= UDC_INCSR_SENDSTALL
|
|
|
|
stalling[index] = true
|
|
|
|
while stalling[index]:
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("stalling\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
Iris::register_interrupt (IRQ_UDC)
|
|
|
|
Iris::wait_for_interrupt (IRQ_UDC)
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("stalling interrupt\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
unsigned usb = UDC_INTRUSB
|
|
|
|
unsigned in = UDC_INTRIN
|
2010-09-09 22:48:35 +03:00
|
|
|
if in & 4:
|
|
|
|
//kdebug ("stall has been sent to in endpoint\n")
|
|
|
|
UDC_INDEX = 2
|
|
|
|
UDC_INCSR &= ~UDC_INCSR_SENTSTALL
|
|
|
|
//Iris::debug ("csr: %x\n", UDC_INCSR)
|
2010-09-08 19:08:57 +03:00
|
|
|
if usb & 4 || in & 1:
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("stuff\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
if !handle_interrupt (usb & 4, in & 1):
|
|
|
|
return
|
|
|
|
unsigned out = UDC_INTROUT
|
|
|
|
if out & 2:
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("stall has been sent to out endpoint\n")
|
|
|
|
UDC_INDEX = 1
|
|
|
|
UDC_OUTCSR &= ~UDC_OUTCSR_SENTSTALL
|
2010-09-08 19:08:57 +03:00
|
|
|
UDC_INDEX = index
|
|
|
|
if index == 2:
|
|
|
|
status = error
|
|
|
|
send_csw ()
|
2010-09-02 00:27:14 +03:00
|
|
|
|
|
|
|
unsigned Udc::big_endian (unsigned src):
|
|
|
|
return src >> 24 | src >> 8 & 0xff00 | src << 8 & 0xff0000 | src << 24
|
|
|
|
|
2010-09-08 19:08:57 +03:00
|
|
|
void Udc::irq_out ():
|
|
|
|
UDC_INDEX = 1
|
|
|
|
unsigned csr = UDC_OUTCSR
|
|
|
|
unsigned size = UDC_OUTCOUNT
|
|
|
|
if !(csr & UDC_OUTCSR_OUTPKTRDY):
|
|
|
|
// No packet, just a notification.
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("no packet\n")
|
2010-09-08 19:08:57 +03:00
|
|
|
return
|
|
|
|
if csr & UDC_OUTCSR_SENDSTALL:
|
|
|
|
// When stalling, do nothing else.
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("not responding to out during stall\n")
|
|
|
|
UDC_OUTCSR = csr & ~UDC_OUTCSR_SENTSTALL
|
2010-09-08 19:08:57 +03:00
|
|
|
return
|
|
|
|
// expect a new cbw.
|
|
|
|
if size != 31:
|
|
|
|
Iris::debug ("count %d != 31\n", size)
|
|
|
|
stall (2)
|
|
|
|
return
|
|
|
|
union Cbw:
|
|
|
|
unsigned u[8]
|
2010-09-09 22:48:35 +03:00
|
|
|
char b[32]
|
2010-09-08 19:08:57 +03:00
|
|
|
CBW cbw
|
|
|
|
Cbw cbw
|
2010-09-09 22:48:35 +03:00
|
|
|
for unsigned i = 0; i < 7; ++i:
|
2010-09-08 19:08:57 +03:00
|
|
|
cbw.u[i] = UDC_FIFO (1)
|
2010-09-09 22:48:35 +03:00
|
|
|
for unsigned i = 28; i < 31; ++i:
|
|
|
|
cbw.b[i] = UDC_FIFO8 (1)
|
|
|
|
UDC_OUTCSR = csr & ~UDC_OUTCSR_OUTPKTRDY
|
2010-09-08 19:08:57 +03:00
|
|
|
tag = cbw.cbw.tag
|
|
|
|
if cbw.cbw.sig != 0x43425355 || cbw.cbw.lun != 0 || cbw.cbw.size == 0 || cbw.cbw.size > 16:
|
|
|
|
Iris::debug ("sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size)
|
|
|
|
stall (2)
|
|
|
|
return
|
2010-09-09 22:48:35 +03:00
|
|
|
//kdebug ("bulk cbw\t")
|
2010-09-02 00:27:14 +03:00
|
|
|
UDC_INDEX = 2
|
|
|
|
bool to_host = cbw.cbw.flags & 0x80
|
|
|
|
switch cbw.cbw.data[0]:
|
2010-09-09 22:48:35 +03:00
|
|
|
case CBW::TEST_UNIT_READY:
|
|
|
|
if to_host || cbw.cbw.length != 0:
|
2010-09-08 19:08:57 +03:00
|
|
|
stall (2)
|
2010-09-09 22:48:35 +03:00
|
|
|
return
|
|
|
|
//Iris::debug ("sending ready response\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
send_csw ()
|
|
|
|
break
|
2010-09-09 22:48:35 +03:00
|
|
|
case CBW::REQUEST_SENSE:
|
|
|
|
//Iris::debug ("sense requested\t")
|
|
|
|
send_padded ("\xf0\x00\x05\x00\x00\x00\x00\x00", 8, cbw.cbw.length)
|
|
|
|
send_csw ()
|
|
|
|
break
|
|
|
|
case CBW::FORMAT_UNIT:
|
|
|
|
Iris::panic (0, "FORMAT_UNIT isn't implemented")
|
|
|
|
case CBW::INQUIRY:
|
|
|
|
if !to_host:
|
2010-09-08 19:08:57 +03:00
|
|
|
stall (2)
|
2010-09-02 00:27:14 +03:00
|
|
|
return
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("sending inquiry response\t")
|
|
|
|
send_padded ("\x00\x00\x04\x02\x1f\x00\x00\x00shevek iris usb stick \x00\x00\x04\x02", 36, cbw.cbw.length)
|
2010-09-02 00:27:14 +03:00
|
|
|
send_csw ()
|
2010-09-08 19:08:57 +03:00
|
|
|
break
|
2010-09-09 22:48:35 +03:00
|
|
|
case CBW::RESERVE6:
|
|
|
|
Iris::panic (0, "RESERVE6 isn't implemented")
|
|
|
|
case CBW::RELEASE6:
|
|
|
|
Iris::panic (0, "RELEASE6 isn't implemented")
|
|
|
|
case CBW::SEND_DIAGNOSTIC:
|
|
|
|
Iris::panic (0, "SEND_DIAGNOSTIC isn't implemented")
|
2010-09-02 00:27:14 +03:00
|
|
|
case CBW::READ_CAPACITY:
|
|
|
|
if !to_host:
|
2010-09-08 19:08:57 +03:00
|
|
|
stall (2)
|
2010-09-09 22:48:35 +03:00
|
|
|
return
|
2010-09-02 00:27:14 +03:00
|
|
|
unsigned capacity[2]
|
|
|
|
capacity[0] = big_endian ((block.get_size ().value () >> block_bits) - 1)
|
|
|
|
capacity[1] = big_endian (1 << block_bits)
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("sending capacity: %x * %x\t", capacity[0], capacity[1])
|
2010-09-08 19:08:57 +03:00
|
|
|
send_padded ((char *)capacity, 8, cbw.cbw.length)
|
|
|
|
send_csw ()
|
|
|
|
break
|
2010-09-09 22:48:35 +03:00
|
|
|
case CBW::READ10:
|
|
|
|
unsigned lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5]
|
|
|
|
unsigned blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8]
|
|
|
|
for unsigned i = 0; i < blocks; ++i:
|
|
|
|
//Iris::debug ("reading block %d:", lba + i)
|
|
|
|
// read block lba + i.
|
|
|
|
buffer_page.set_flags (Iris::Page::FRAME)
|
|
|
|
block.get_block (lba << block_bits, 1 << block_bits, 0, buffer_page)
|
|
|
|
for unsigned p = 0; p < 1 << block_bits; p += max_packet_size_bulk:
|
|
|
|
//Iris::debug (" %d", p)
|
|
|
|
UDC_INDEX = 2
|
|
|
|
for unsigned t = 0; t < max_packet_size_bulk; t += 4:
|
|
|
|
UDC_FIFO (2) = ((unsigned *)buffer)[(p + t) >> 2]
|
|
|
|
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
|
|
|
//Iris::debug ("\n")
|
|
|
|
while true:
|
|
|
|
Iris::register_interrupt (IRQ_UDC)
|
|
|
|
Iris::wait_for_interrupt (IRQ_UDC)
|
|
|
|
//kdebug ("interrupt read10\t")
|
|
|
|
unsigned usb = UDC_INTRUSB
|
|
|
|
unsigned in = UDC_INTRIN
|
|
|
|
unsigned out = UDC_INTROUT
|
|
|
|
if usb & 4 || in & 1:
|
|
|
|
//kdebug ("general interrupt read10\t")
|
|
|
|
if !handle_interrupt (usb & 4, in & 1):
|
|
|
|
return
|
|
|
|
if out & 2:
|
|
|
|
Iris::panic (0, "out interrupt while waiting for in")
|
|
|
|
if in & 4:
|
|
|
|
break
|
2010-09-08 19:08:57 +03:00
|
|
|
send_csw ()
|
|
|
|
break
|
2010-09-09 22:48:35 +03:00
|
|
|
case CBW::WRITE10:
|
|
|
|
Iris::panic (0, "WRITE10 isn't implemented")
|
|
|
|
case CBW::RESERVE10:
|
|
|
|
Iris::panic (0, "RESERVE10 isn't implemented")
|
|
|
|
case CBW::RELEASE10:
|
|
|
|
Iris::panic (0, "RELEASE10 isn't implemented")
|
2010-09-02 00:27:14 +03:00
|
|
|
default:
|
|
|
|
Iris::debug ("cbw:")
|
|
|
|
for unsigned i = 0; i < cbw.cbw.size; ++i:
|
|
|
|
kdebug_char (' ')
|
|
|
|
kdebug_num (cbw.cbw.data[i], 2)
|
|
|
|
Iris::debug ("\n")
|
|
|
|
residue = cbw.cbw.length
|
2010-09-08 19:08:57 +03:00
|
|
|
stall (1)
|
2010-09-09 22:48:35 +03:00
|
|
|
return
|
2010-09-08 19:08:57 +03:00
|
|
|
// TODO.
|
2010-09-02 00:27:14 +03:00
|
|
|
|
2010-09-08 19:08:57 +03:00
|
|
|
bool Udc::handle_interrupt (bool usb, bool in):
|
|
|
|
if usb:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("usb\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
// reset.
|
|
|
|
irq_usb ()
|
|
|
|
return false
|
|
|
|
if in:
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("control\t")
|
2010-09-08 19:08:57 +03:00
|
|
|
// control request
|
|
|
|
irq_in0 ()
|
|
|
|
return true
|
2010-09-02 00:27:14 +03:00
|
|
|
|
|
|
|
void Udc::interrupt ():
|
2010-09-09 22:48:35 +03:00
|
|
|
//Iris::debug ("interrupt\n")
|
2010-09-02 00:27:14 +03:00
|
|
|
while true:
|
|
|
|
unsigned usb = UDC_INTRUSB
|
|
|
|
unsigned in = UDC_INTRIN
|
2010-09-09 22:48:35 +03:00
|
|
|
bool action = false
|
2010-09-02 00:27:14 +03:00
|
|
|
if in & 4:
|
2010-09-09 22:48:35 +03:00
|
|
|
Iris::panic (0, "data request during idle\n")
|
|
|
|
if usb & 4 || in & 1:
|
|
|
|
handle_interrupt (usb & 4, in & 1)
|
|
|
|
action = true
|
|
|
|
unsigned out = UDC_INTROUT
|
2010-09-02 00:27:14 +03:00
|
|
|
if out & 2:
|
|
|
|
irq_out ()
|
2010-09-09 22:48:35 +03:00
|
|
|
action = true
|
|
|
|
if !action:
|
|
|
|
// No more interrupts to handle; this is normal, because we're looping until this happens.
|
|
|
|
//Iris::debug ("irq done\n")
|
|
|
|
return
|
2010-09-02 00:27:14 +03:00
|
|
|
|
|
|
|
Iris::Num start ():
|
|
|
|
map_udc ()
|
|
|
|
map_gpio ()
|
|
|
|
map_cpm ()
|
|
|
|
Udc udc
|
|
|
|
|
|
|
|
Iris::WBlock nand = Iris::my_parent.get_capability <Iris::WBlock> ()
|
|
|
|
udc.init (nand)
|
|
|
|
while true:
|
|
|
|
Iris::register_interrupt (IRQ_UDC)
|
|
|
|
Iris::wait ()
|
|
|
|
udc.interrupt ()
|