2009-09-27 11:23:33 +03:00
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OUTPUT_ARCH(mips)
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ENTRY(__start)
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MEMORY
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{
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2012-09-26 20:03:36 +03:00
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ram : ORIGIN = 0x80003000 , LENGTH = 0x800
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2009-09-27 11:23:33 +03:00
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}
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SECTIONS
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{
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. = ALIGN(4);
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.text : { *(.text*) } > ram
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. = ALIGN(4);
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2012-09-26 23:20:38 +03:00
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.rodata : { *(.rodata*) *(.note*) } > ram
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2009-09-27 11:23:33 +03:00
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. = ALIGN(4);
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.sdata : { *(.sdata*) } > ram
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. = ALIGN(4);
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.data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
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_gp = ABSOLUTE(.); /* Base of small data */
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.got : { *(.got*) } > ram
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. = ALIGN(4);
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.sbss : { *(.sbss*) } > ram
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.bss : { *(.bss*) } > ram
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. = ALIGN (4);
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}
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