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iris/mips/interrupts.ccp

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#pypp 0
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// Iris: micro-kernel for a capability-based operating system.
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// mips/interrupts.ccp: Functions called by mips/entry.S.
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// Copyright 2009 Bas Wijnen <wijnen@debian.org>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
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#define ARCH
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#include "../kernel.hh"
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typedef unsigned cacheline[8]
void arch_flush_cache ():
for cacheline *line = (cacheline *)0x80000000; line < (cacheline *)0x80008000; ++line:
__asm__ volatile ("lw $k0, %0; cache 0, 0($k0); cache 1, 0($k0)" :: "m"(line))
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static void handle_exit (Thread *old_current):
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if !current || (current == &idle):
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schedule ()
if !current:
current = &idle
if old_current == current:
return
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arch_flush_cache ()
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if current != &idle:
if (Memory *)asids[current->address_space->arch.asid] != current->address_space:
if asids[0]:
current->address_space->arch.asid = asids[0]
asids[0] = asids[asids[0]]
else:
static unsigned random = 1
current->address_space->arch.asid = random
// Overwrite used asid, so flush those values from tlb.
flush_tlb (random)
++random
if random >= 64:
random = 1
asids[current->address_space->arch.asid] = (unsigned)current->address_space
cp0_set (CP0_ENTRY_HI, current->address_space->arch.asid)
directory = current->address_space->arch.directory
if current->flags & THREAD_FLAG_PRIV:
cp0_set (CP0_STATUS, 0x1000ff13)
else:
cp0_set (CP0_STATUS, 0x0000ff13)
/// A TLB miss has occurred. This is the slow version. It is only used
/// when k0 or k1 is not 0, or when an error occurs.
/// Otherwise, the ultra-fast code in entry.S is used.
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Thread *tlb_refill ():
//panic (0x88776655, "TLB refill")
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Thread *old_current = current
if !directory:
panic (0x44449999, "No directory")
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unsigned EntryHi
cp0_get (CP0_ENTRY_HI, EntryHi)
unsigned *t = directory[EntryHi >> 21]
if !t:
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unsigned a
cp0_get (CP0_EPC, a)
dbg_send (a)
cp0_get (CP0_BAD_V_ADDR, a)
dbg_send (a)
panic (0x99992222, "No page table")
// - 2 instead of - 1 means reset bit 0
unsigned idx = (EntryHi >> 12) & ((1 << 9) - 2)
cp0_set (CP0_ENTRY_LO0, t[idx])
cp0_set (CP0_ENTRY_LO1, t[idx + 1])
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__asm__ volatile ("tlbwr")
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handle_exit (old_current)
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return current
/// An interrupt which is not an exception has occurred.
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Thread *interrupt ():
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//panic (0x88877722, "Interrupt")
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Thread *old_current = current
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unsigned ipr = INTC_IPR
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for unsigned i = 0; i < 32; ++i:
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if ipr & (1 << i):
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// Handle timer interrupts specially: don't disable them.
if i == IRQ_OST0:
continue
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// Disable the interrupt while handling it.
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intc_mask_irq (i)
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intc_ack_irq (i)
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// Send message to interrupt handler.
if arch_interrupt_receiver[i]:
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Capability::Context c
for unsigned j = 0; j < 4; ++j:
c.data[j] = 0
c.cap[j] = NULL
c.copy[j] = false
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dbg_code = (unsigned)arch_interrupt_receiver[i]->owner
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arch_interrupt_receiver[i]->send_message (i, &c)
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if ipr & (1 << IRQ_OST0):
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ost_clear_uf (0)
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intc_ack_irq (IRQ_OST0)
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timer_interrupt ()
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handle_exit (old_current)
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return current
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void flush_tlb (unsigned asid):
for unsigned tlb = 1; tlb < 32; ++tlb:
cp0_set (CP0_INDEX, tlb)
__asm__ volatile ("tlbr")
unsigned hi
cp0_get (CP0_ENTRY_HI, hi)
if (hi & 0x1f) == asid:
// Set asid to 0, which is only used by the idle task.
cp0_set (CP0_ENTRY_HI, 0x2000 * tlb)
__asm__ volatile ("tlbwi")
static void arch_invoke ():
Capability *target
bool wait
Thread *caller = current
target = caller->address_space->find_capability (caller->arch.v0, &wait)
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do_schedule = false
if wait:
caller->wait ()
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if !target:
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// There must be no action here.
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else:
Capability::Context c
c.cap[0] = caller->address_space->find_capability (caller->arch.a0, &c.copy[0])
c.cap[1] = caller->address_space->find_capability (caller->arch.a1, &c.copy[1])
c.cap[2] = caller->address_space->find_capability (caller->arch.a2, &c.copy[2])
c.cap[3] = caller->address_space->find_capability (caller->arch.a3, &c.copy[3])
c.data[0] = caller->arch.t0
c.data[1] = caller->arch.t1
c.data[2] = caller->arch.t2
c.data[3] = caller->arch.t3
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target->invoke (&c)
// If the caller received a reply from the kernel, it is no longer set as current. Don't let it lose its timeslice.
if caller != current && (caller->flags & (THREAD_FLAG_RUNNING | THREAD_FLAG_WAITING)) == THREAD_FLAG_RUNNING && !do_schedule:
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current = caller
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/// A general exception has occurred.
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Thread *exception ():
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Thread *old_current = current
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unsigned cause
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cp0_get (CP0_CAUSE, cause)
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switch (cause >> 2) & 0x1f:
case 0:
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// Interrupt. This shouldn't happen, since CAUSE[IV] == 1.
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panic (0x01223344, "Interrupt on exception vector.")
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case 1:
// TLB modification.
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panic (0x11223344, "TLB modification.")
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case 2:
// TLB load or instruction fetch.
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unsigned a
cp0_get (CP0_EPC, a)
dbg_send (a)
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panic (0x21223344, "TLB load or instruction fetch.")
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case 3:
// TLB store.
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unsigned a
cp0_get (CP0_EPC, a)
dbg_send (a)
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cp0_get (CP0_BAD_V_ADDR, a)
dbg_send (a)
panic (0x31223344, "TLB store.")
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case 4:
// Address error load or instruction fetch.
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unsigned a
cp0_get (CP0_EPC, a)
dbg_send (a)
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cp0_get (CP0_BAD_V_ADDR, a)
dbg_send (a)
panic (0x41223344, "Address error load or instruction fetch.")
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case 5:
// Address error store.
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dbg_send (current->arch.v1, 4)
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unsigned a
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cp0_get (CP0_EPC, a)
dbg_send (*(unsigned *)(a & ~3), 32)
dbg_send (a, 32)
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cp0_get (CP0_BAD_V_ADDR, a)
dbg_send (a, 32)
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panic (0x51223344, "Address error store.")
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case 6:
// Bus error instruction fetch.
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panic (0x61223344, "Bus error instruction fetch.")
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case 7:
// Bus error load or store.
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panic (0x71223344, "Bus error load or store.")
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case 8:
// Syscall.
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current->pc += 4
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arch_invoke ()
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break
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case 9:
// Breakpoint.
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//panic (0x91223344, "Breakpoint.")
dbg_send (current->arch.a0, current->arch.a1)
current->pc += 4
break
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case 10:
// Reserved instruction.
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panic (0xa1223344, "Reserved instruction.")
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case 11:
// Coprocessor unusable.
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panic (0xb1223344, "Coprocessor unusable.")
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case 12:
// Arithmetic overflow.
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panic (0xc1223344, "Arithmetic overflow.")
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case 13:
// Trap.
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panic (0xd1223344, "Trap.")
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case 15:
// Floating point exception.
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panic (0xe1223344, "Floating point exception.")
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case 23:
// Reference to WatchHi/WatchLo address.
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panic (0xf1223344, "Reference to WatchHi/WatchLo address.")
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case 24:
// Machine check.
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panic (0xf3223344, "Machine check.")
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case 30:
// Cache error (EJTAG only).
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panic (0xf4223344, "Cache error (EJTAG only).")
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case 14:
case 16:
case 17:
case 18:
case 19:
case 20:
case 21:
case 22:
case 25:
case 26:
case 27:
case 28:
case 29:
case 31:
// Reserved.
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panic (0xf5223344, "Reserved exception code")
default:
panic (0xf6223344, "Impossible exception code")
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handle_exit (old_current)
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return current
/// There's a cache error. Big trouble. Probably not worth trying to recover.
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Thread *cache_error ():
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panic (0x33333333, "cache error")
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Thread *old_current = current
handle_exit (old_current)
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return current