iris/mips/nanonote/stage1.ld

OUTPUT_ARCH(mips)
ENTRY(__start)
MEMORY
{
	ram	: ORIGIN = 0x80003000 , LENGTH = 0x800
}

SECTIONS
{
	/* Start with the part containing the interrupt and exception code. */
	.text : { mips/board/mips_board_stage1_elf-stage1.o(.text*) } > ram
	.text : { *(.text*) } > ram

	.rodata : { *(.rodata*) *(.note*) } > ram
	.sdata : { *(.sdata*) } > ram
	.data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram

	_gp = ABSOLUTE(.);

	.got : { *(.got*) } > ram
	.sbss : { *(.sbss*) } > ram
	.bss : { *(.bss*) } > ram
}