From 1bb67efc75413b68c98a2225e41edf6b9e71b570 Mon Sep 17 00:00:00 2001 From: Bas Wijnen Date: Wed, 10 Jun 2009 21:42:01 +0200 Subject: [PATCH] working on lcd --- boot-programs/gpio.txt | 293 +- boot-programs/jz4730.hhp | 3901 +++++++++++++++++++ boot-programs/{thread0.ccp => keyboard.ccp} | 0 boot-programs/lcd.ccp | 326 ++ boot-programs/thread1.ccp | 23 - invoke.ccp | 141 +- iris.h | 49 +- mips/Makefile.arch | 2 +- mips/arch.ccp | 1 + 9 files changed, 4470 insertions(+), 266 deletions(-) create mode 100644 boot-programs/jz4730.hhp rename boot-programs/{thread0.ccp => keyboard.ccp} (100%) create mode 100644 boot-programs/lcd.ccp delete mode 100644 boot-programs/thread1.ccp diff --git a/boot-programs/gpio.txt b/boot-programs/gpio.txt index ee11be7..41dfdf2 100644 --- a/boot-programs/gpio.txt +++ b/boot-programs/gpio.txt @@ -183,131 +183,168 @@ do { \ // Pins on the trendtac: -0 keyboard -1 keyboard -2 keyboard -3 keyboard -4 keyboard -5 keyboard -6 keyboard -7 keyboard -8 keyboard interrupt -9 -10 -11 -12 -13 touchpad right button -14 -15 -16 touchpad left button -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 -91 -92 -93 -94 -95 -96 keyboard -97 keyboard -98 keyboard -99 keyboard -100 keyboard -101 keyboard -102 keyboard -103 keyboard -104 keyboard -105 keyboard -106 keyboard -107 keyboard -108 keyboard -109 keyboard -110 keyboard -111 keyboard -112 -113 -114 -115 -116 -117 -118 -119 -120 -121 -122 -123 -124 -125 keyboard -126 -127 +0.00 keyboard +0.01 keyboard +0.02 keyboard +0.03 keyboard +0.04 keyboard +0.05 keyboard +0.06 keyboard +0.07 keyboard +0.08 keyboard interrupt? +0.09 +0.10 +0.11 +0.12 +0.13 touchpad right button +0.14 +0.15 +0.16 touchpad left button +0.17 +0.18 +0.19 +0.20 +0.21 +0.22 +0.23 +0.24 +0.25 +0.26 +0.27 +0.28 +0.29 +0.30 +0.31 +1.00 +1.01 +1.02 +1.03 +1.04 +1.05 +1.06 +1.07 +1.08 +1.09 +1.10 +1.11 +1.12 +1.13 +1.14 +1.15 +1.16 +1.17 +1.18 +1.19 +1.20 +1.21 +1.22 +1.23 +1.24 +1.25 +1.26 +1.27 +1.28 +1.29 +1.30 +1.31 +2.00 SPEN: lcd enable +2.01 SPCK: lcd clock +2.02 SPDA: lcd data +2.03 LCD_RET: lcd reset +2.04 +2.05 +2.06 +2.07 +2.08 +2.09 +2.10 +2.11 +2.12 +2.13 +2.14 +2.15 +2.16 +2.17 +2.18 +2.19 +2.20 +2.21 +2.22 +2.23 +2.24 +2.25 +2.26 +2.27 +2.28 +2.29 +2.30 PWM enable (for lcd backlight) +2.31 +3.00 keyboard +3.01 keyboard +3.02 keyboard +3.03 keyboard +3.04 keyboard +3.05 keyboard +3.06 keyboard +3.07 keyboard +3.08 keyboard +3.09 keyboard +3.10 keyboard +3.11 keyboard +3.12 keyboard +3.13 keyboard +3.14 keyboard +3.15 keyboard +3.16 +3.17 +3.18 +3.19 +3.20 +3.21 +3.22 +3.23 +3.24 +3.25 +3.26 +3.27 +3.28 +3.29 keyboard +3.30 +3.31 + +Devices enabled in linux: ++ __harb_usb0_uhc(); ++ __gpio_as_emc(); ++ __gpio_as_uart0(); ++ __gpio_as_dma(); ++ __gpio_as_eth(); ++ __gpio_as_usb(); ++ __gpio_as_lcd_master(); ++#if defined(CONFIG_I2S_AK4642EN) ++//wjx __gpio_as_scc1(); ++ __gpio_as_i2s_master(); //wjx ++#endif ++#if defined(CONFIG_I2S_TSC2301) || defined(CONFIG_I2S_TLC320AIC23) ++ __gpio_as_ssi(); ++#endif ++ //__gpio_as_ac97(); ++#if defined(CONFIG_I2S_TSC2301) || defined(CONFIG_I2S_TLC320AIC23) || defined(CONFIG_I2S_CS42L51) ++ __gpio_as_i2s_slave(); ++#endif ++//wjx __gpio_as_cim(); ++ __gpio_as_msc(); ++ ++/* wjx ++ __gpio_as_output(GPIO_LED_EN); ++ __gpio_set_pin(GPIO_LED_EN); ++ ++ __gpio_as_output(GPIO_DISP_OFF_N); ++ __gpio_set_pin(GPIO_DISP_OFF_N); ++*/ ++ __gpio_as_output(GPIO_PWM0); ++ __gpio_set_pin(GPIO_PWM0); ++ ++ ++//wjx __gpio_as_input(GPIO_RTC_IRQ); ++ __gpio_as_output(GPIO_USB_CLK_EN); ++ __gpio_set_pin(GPIO_USB_CLK_EN); diff --git a/boot-programs/jz4730.hhp b/boot-programs/jz4730.hhp new file mode 100644 index 0000000..7925f76 --- /dev/null +++ b/boot-programs/jz4730.hhp @@ -0,0 +1,3901 @@ +#ifndef __JZ4730_HH__ +#define __JZ4730_HH__ + +#include + +// Base addresses are the place where the pages are mapped. +#define HARB_BASE 0x00000000 +#define EMC_BASE 0x00001000 +#define DMAC_BASE 0x00002000 +#define UHC_BASE 0x00003000 +#define UDC_BASE 0x00004000 +#define LCD_BASE 0x00005000 +#define CIM_BASE 0x00006000 +#define ETH_BASE 0x00007000 +#define NBM_BASE 0x00008000 +#define CPM_BASE 0x00009000 +#define INTC_BASE 0x0000a000 +#define OST_BASE 0x0000b000 +#define RTC_BASE 0x0000c000 +#define WDT_BASE 0x0000d000 +#define GPIO_BASE 0x0000e000 +#define AIC_BASE 0x0000f000 +#define MSC_BASE 0x00010000 +#define UART0_BASE 0x00011000 +#define UART1_BASE 0x00012000 +#define UART2_BASE 0x00013000 +#define UART3_BASE 0x00014000 +#define FIR_BASE 0x00015000 +#define SCC_BASE 0x00016000 +#define SCC0_BASE 0x00017000 +#define I2C_BASE 0x00018000 +#define SSI_BASE 0x00019000 +#define SCC1_BASE 0x0001a000 +#define PWM0_BASE 0x0001b000 +#define PWM1_BASE 0x0001c000 +#define DES_BASE 0x0001d000 +#define UPRT_BASE 0x0001e000 +#define KBC_BASE 0x0001f000 + +// Physical addresses are where they really are. +// (In kernel space you need to add 0xa0000000 to see them unmapped uncached in kseg2.) +#define HARB_PHYSICAL 0x13000000 +#define EMC_PHYSICAL 0x13010000 +#define DMAC_PHYSICAL 0x13020000 +#define UHC_PHYSICAL 0x13030000 +#define UDC_PHYSICAL 0x13040000 +#define LCD_PHYSICAL 0x13050000 +#define CIM_PHYSICAL 0x13060000 +#define ETH_PHYSICAL 0x13100000 +#define NBM_PHYSICAL 0x13F00000 +#define CPM_PHYSICAL 0x10000000 +#define INTC_PHYSICAL 0x10001000 +#define OST_PHYSICAL 0x10002000 +#define RTC_PHYSICAL 0x10003000 +#define WDT_PHYSICAL 0x10004000 +#define GPIO_PHYSICAL 0x10010000 +#define AIC_PHYSICAL 0x10020000 +#define MSC_PHYSICAL 0x10021000 +#define UART0_PHYSICAL 0x10030000 +#define UART1_PHYSICAL 0x10031000 +#define UART2_PHYSICAL 0x10032000 +#define UART3_PHYSICAL 0x10033000 +#define FIR_PHYSICAL 0x10040000 +#define SCC_PHYSICAL 0x10041000 +#define SCC0_PHYSICAL 0x10041000 +#define I2C_PHYSICAL 0x10042000 +#define SSI_PHYSICAL 0x10043000 +#define SCC1_PHYSICAL 0x10044000 +#define PWM0_PHYSICAL 0x10050000 +#define PWM1_PHYSICAL 0x10051000 +#define DES_PHYSICAL 0x10060000 +#define UPRT_PHYSICAL 0x10061000 +#define KBC_PHYSICAL 0x10062000 + +// Map IO memory (requires a priviledged __my_thread capability). +static void __map_io (unsigned physical, unsigned mapping): + Capability page = memory_create_page (__my_memory) + // 0 means not cachable. + alloc_physical (page, physical, 0) + // 1 means writable. + memory_map (__my_memory, page, mapping, 1) + //drop (page) + +// Physical addresses are where they really are. +#define map_harb() do { __map_io (HARB_PHYSICAL, HARB_BASE); } while (0) +#define map_emc() do { __map_io (EMC_PHYSICAL, EMC_BASE); } while (0) +#define map_dmac() do { __map_io (DMAC_PHYSICAL, DMAC_BASE); } while (0) +#define map_uhc() do { __map_io (UHC_PHYSICAL, UHC_BASE); } while (0) +#define map_udc() do { __map_io (UDC_PHYSICAL, UDC_BASE); } while (0) +#define map_lcd() do { __map_io (LCD_PHYSICAL, LCD_BASE); } while (0) +#define map_cim() do { __map_io (CIM_PHYSICAL, CIM_BASE); } while (0) +#define map_eth() do { __map_io (ETH_PHYSICAL, ETH_BASE); } while (0) +#define map_nbm() do { __map_io (NBM_PHYSICAL, NBM_BASE); } while (0) +#define map_cpm() do { __map_io (CPM_PHYSICAL, CPM_BASE); } while (0) +#define map_intc() do { __map_io (INTC_PHYSICAL, INTC_BASE); } while (0) +#define map_ost() do { __map_io (OST_PHYSICAL, OST_BASE); } while (0) +#define map_rtc() do { __map_io (RTC_PHYSICAL, RTC_BASE); } while (0) +#define map_wdt() do { __map_io (WDT_PHYSICAL, WDT_BASE); } while (0) +#define map_gpio() do { __map_io (GPIO_PHYSICAL, GPIO_BASE); } while (0) +#define map_aic() do { __map_io (AIC_PHYSICAL, AIC_BASE); } while (0) +#define map_msc() do { __map_io (MSC_PHYSICAL, MSC_BASE); } while (0) +#define map_uart0() do { __map_io (UART0_PHYSICAL, UART0_BASE); } while (0) +#define map_uart1() do { __map_io (UART1_PHYSICAL, UART1_BASE); } while (0) +#define map_uart2() do { __map_io (UART2_PHYSICAL, UART2_BASE); } while (0) +#define map_uart3() do { __map_io (UART3_PHYSICAL, UART3_BASE); } while (0) +#define map_fir() do { __map_io (FIR_PHYSICAL, FIR_BASE); } while (0) +#define map_scc() do { __map_io (SCC_PHYSICAL, SCC_BASE); } while (0) +#define map_scc0() do { __map_io (SCC0_PHYSICAL, SCC0_BASE); } while (0) +#define map_i2c() do { __map_io (I2C_PHYSICAL, I2C_BASE); } while (0) +#define map_ssi() do { __map_io (SSI_PHYSICAL, SSI_BASE); } while (0) +#define map_scc1() do { __map_io (SCC1_PHYSICAL, SCC1_BASE); } while (0) +#define map_pwm0() do { __map_io (PWM0_PHYSICAL, PWM0_BASE); } while (0) +#define map_pwm1() do { __map_io (PWM1_PHYSICAL, PWM1_BASE); } while (0) +#define map_des() do { __map_io (DES_PHYSICAL, DES_BASE); } while (0) +#define map_uprt() do { __map_io (UPRT_PHYSICAL, UPRT_BASE); } while (0) +#define map_kbc() do { __map_io (KBC_PHYSICAL, KBC_BASE); } while (0) + +/************************************************************************* + * MSC + *************************************************************************/ +#define MSC_STRPCL REG16 (MSC_BASE + 0x000) +#define MSC_STAT REG32 (MSC_BASE + 0x004) +#define MSC_CLKRT REG16 (MSC_BASE + 0x008) +#define MSC_CMDAT REG32 (MSC_BASE + 0x00C) +#define MSC_RESTO REG16 (MSC_BASE + 0x010) +#define MSC_RDTO REG16 (MSC_BASE + 0x014) +#define MSC_BLKLEN REG16 (MSC_BASE + 0x018) +#define MSC_NOB REG16 (MSC_BASE + 0x01C) +#define MSC_SNOB REG16 (MSC_BASE + 0x020) +#define MSC_IMASK REG16 (MSC_BASE + 0x024) +#define MSC_IREG REG16 (MSC_BASE + 0x028) +#define MSC_CMD REG8 (MSC_BASE + 0x02C) +#define MSC_ARG REG32 (MSC_BASE + 0x030) +#define MSC_RES REG16 (MSC_BASE + 0x034) +#define MSC_RXFIFO REG32 (MSC_BASE + 0x038) +#define MSC_TXFIFO REG32 (MSC_BASE + 0x03C) + +/* MSC Clock and Control Register (MSC_STRPCL) */ + +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) +#define MSC_STRPCL_START_READWAIT (1 << 5) +#define MSC_STRPCL_STOP_READWAIT (1 << 4) +#define MSC_STRPCL_RESET (1 << 3) +#define MSC_STRPCL_START_OP (1 << 2) +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) + #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ + #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ + +/* MSC Status Register (MSC_STAT) */ + +#define MSC_STAT_IS_RESETTING (1 << 15) +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) +#define MSC_STAT_PRG_DONE (1 << 13) +#define MSC_STAT_DATA_TRAN_DONE (1 << 12) +#define MSC_STAT_END_CMD_RES (1 << 11) +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) +#define MSC_STAT_IS_READWAIT (1 << 9) +#define MSC_STAT_CLK_EN (1 << 8) +#define MSC_STAT_DATA_FIFO_FULL (1 << 7) +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) +#define MSC_STAT_CRC_RES_ERR (1 << 5) +#define MSC_STAT_CRC_READ_ERROR (1 << 4) +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) + #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ + #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ + #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ +#define MSC_STAT_TIME_OUT_RES (1 << 1) +#define MSC_STAT_TIME_OUT_READ (1 << 0) + +/* MSC Bus Clock Control Register (MSC_CLKRT) */ + +#define MSC_CLKRT_CLK_RATE_BIT 0 +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) + #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ + #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ + +/* MSC Command Sequence Control Register (MSC_CMDAT) */ + +#define MSC_CMDAT_IO_ABORT (1 << 11) +#define MSC_CMDAT_BUS_WIDTH_BIT 9 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) + #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ + #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ + #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) + #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) +#define MSC_CMDAT_DMA_EN (1 << 8) +#define MSC_CMDAT_INIT (1 << 7) +#define MSC_CMDAT_BUSY (1 << 6) +#define MSC_CMDAT_STREAM_BLOCK (1 << 5) +#define MSC_CMDAT_WRITE (1 << 4) +#define MSC_CMDAT_READ (0 << 4) +#define MSC_CMDAT_DATA_EN (1 << 3) +#define MSC_CMDAT_RESPONSE_BIT 0 +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) + #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ + #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ + #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ + #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ + #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ + #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ + #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ + +#define CMDAT_DMA_EN (1 << 8) +#define CMDAT_INIT (1 << 7) +#define CMDAT_BUSY (1 << 6) +#define CMDAT_STREAM (1 << 5) +#define CMDAT_WRITE (1 << 4) +#define CMDAT_DATA_EN (1 << 3) + +/* MSC Interrupts Mask Register (MSC_IMASK) */ + +#define MSC_IMASK_SDIO (1 << 7) +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) +#define MSC_IMASK_END_CMD_RES (1 << 2) +#define MSC_IMASK_PRG_DONE (1 << 1) +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) + + +/* MSC Interrupts Status Register (MSC_IREG) */ + +#define MSC_ISDIO (1 << 7) +#define MSC_ITXFIFO_WR_REQ (1 << 6) +#define MSC_IRXFIFO_RD_REQ (1 << 5) +#define MSC_IEND_CMD_RES (1 << 2) +#define MSC_IPRG_DONE (1 << 1) +#define MSC_IDATA_TRAN_DONE (1 << 0) + + + + +/************************************************************************* + * RTC + *************************************************************************/ +#define RTC_RCR REG32 (RTC_BASE + 0x00) +#define RTC_RSR REG32 (RTC_BASE + 0x04) +#define RTC_RSAR REG32 (RTC_BASE + 0x08) +#define RTC_RGR REG32 (RTC_BASE + 0x0c) + +#define RTC_RCR_HZ (1 << 6) +#define RTC_RCR_HZIE (1 << 5) +#define RTC_RCR_AF (1 << 4) +#define RTC_RCR_AIE (1 << 3) +#define RTC_RCR_AE (1 << 2) +#define RTC_RCR_START (1 << 0) + +#define RTC_RGR_LOCK (1 << 31) +#define RTC_RGR_ADJ_BIT 16 +#define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) +#define RTC_RGR_DIV_BIT 0 +#define RTC_DIV_MASK (0xff << RTC_RGR_DIV_BIT) + + + + +/************************************************************************* + * FIR + *************************************************************************/ +#define FIR_TDR REG8 (FIR_BASE + 0x000) +#define FIR_RDR REG8 (FIR_BASE + 0x004) +#define FIR_TFLR REG16 (FIR_BASE + 0x008) +#define FIR_AR REG8 (FIR_BASE + 0x00C) +#define FIR_CR1 REG8 (FIR_BASE + 0x010) +#define FIR_CR2 REG16 (FIR_BASE + 0x014) +#define FIR_SR REG16 (FIR_BASE + 0x018) + +/* FIR Control Register 1 (FIR_CR1) */ + +#define FIR_CR1_FIRUE (1 << 7) +#define FIR_CR1_ACE (1 << 6) +#define FIR_CR1_EOUS (1 << 5) +#define FIR_CR1_TIIE (1 << 4) +#define FIR_CR1_TFIE (1 << 3) +#define FIR_CR1_RFIE (1 << 2) +#define FIR_CR1_TXE (1 << 1) +#define FIR_CR1_RXE (1 << 0) + +/* FIR Control Register 2 (FIR_CR2) */ + +#define FIR_CR2_SIPE (1 << 10) +#define FIR_CR2_BCRC (1 << 9) +#define FIR_CR2_TFLRS (1 << 8) +#define FIR_CR2_ISS (1 << 7) +#define FIR_CR2_LMS (1 << 6) +#define FIR_CR2_TPPS (1 << 5) +#define FIR_CR2_RPPS (1 << 4) +#define FIR_CR2_TTRG_BIT 2 +#define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) + #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ + #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ + #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ + #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ +#define FIR_CR2_RTRG_BIT 0 +#define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) + #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ + #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ + #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ + #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ + +/* FIR Status Register (FIR_SR) */ + +#define FIR_SR_RFW (1 << 12) +#define FIR_SR_RFA (1 << 11) +#define FIR_SR_TFRTL (1 << 10) +#define FIR_SR_RFRTL (1 << 9) +#define FIR_SR_URUN (1 << 8) +#define FIR_SR_RFTE (1 << 7) +#define FIR_SR_ORUN (1 << 6) +#define FIR_SR_CRCE (1 << 5) +#define FIR_SR_FEND (1 << 4) +#define FIR_SR_TFF (1 << 3) +#define FIR_SR_RFE (1 << 2) +#define FIR_SR_TIDLE (1 << 1) +#define FIR_SR_RB (1 << 0) + + + + +/************************************************************************* + * SCC + *************************************************************************/ +#define SCC_DR(base) REG8 ((base) + 0x000) +#define SCC_FDR(base) REG8 ((base) + 0x004) +#define SCC_CR(base) REG32 ((base) + 0x008) +#define SCC1_CR(base) REG32 ((base) + 0x008) +#define SCC_SR(base) REG16 ((base) + 0x00C) +#define SCC_TFR(base) REG16 ((base) + 0x010) +#define SCC_EGTR(base) REG8 ((base) + 0x014) +#define SCC_ECR(base) REG32 ((base) + 0x018) +#define SCC_RTOR(base) REG8 ((base) + 0x01C) + +/* SCC FIFO Data Count Register (SCC_FDR) */ + +#define SCC_FDR_EMPTY 0x00 +#define SCC_FDR_FULL 0x10 + +/* SCC Control Register (SCC_CR) */ + +#define SCC_CR_SCCE (1 << 31) +#define SCC_CR_TRS (1 << 30) +#define SCC_CR_T2R (1 << 29) +#define SCC_CR_FDIV_BIT 24 +#define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) + #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ + #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ +#define SCC_CR_FLUSH (1 << 23) +#define SCC_CR_TRIG_BIT 16 +#define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) + #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ + #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ + #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ + #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ +#define SCC_CR_TP (1 << 15) +#define SCC_CR_CONV (1 << 14) +#define SCC_CR_TXIE (1 << 13) +#define SCC_CR_RXIE (1 << 12) +#define SCC_CR_TENDIE (1 << 11) +#define SCC_CR_RTOIE (1 << 10) +#define SCC_CR_ECIE (1 << 9) +#define SCC_CR_EPIE (1 << 8) +#define SCC_CR_RETIE (1 << 7) +#define SCC_CR_EOIE (1 << 6) +#define SCC_CR_TSEND (1 << 3) +#define SCC_CR_PX_BIT 1 +#define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) + #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ + #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ + #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ +#define SCC_CR_CLKSTP (1 << 0) + +/* SCC Status Register (SCC_SR) */ + +#define SCC_SR_TRANS (1 << 15) +#define SCC_SR_ORER (1 << 12) +#define SCC_SR_RTO (1 << 11) +#define SCC_SR_PER (1 << 10) +#define SCC_SR_TFTG (1 << 9) +#define SCC_SR_RFTG (1 << 8) +#define SCC_SR_TEND (1 << 7) +#define SCC_SR_RETR_3 (1 << 4) +#define SCC_SR_ECNTO (1 << 0) + + + + +/************************************************************************* + * ETH + *************************************************************************/ +#define ETH_BMR REG32 (ETH_BASE + 0x1000) +#define ETH_TPDR REG32 (ETH_BASE + 0x1004) +#define ETH_RPDR REG32 (ETH_BASE + 0x1008) +#define ETH_RAR REG32 (ETH_BASE + 0x100C) +#define ETH_TAR REG32 (ETH_BASE + 0x1010) +#define ETH_SR REG32 (ETH_BASE + 0x1014) +#define ETH_CR REG32 (ETH_BASE + 0x1018) +#define ETH_IER REG32 (ETH_BASE + 0x101C) +#define ETH_MFCR REG32 (ETH_BASE + 0x1020) +#define ETH_CTAR REG32 (ETH_BASE + 0x1050) +#define ETH_CRAR REG32 (ETH_BASE + 0x1054) +#define ETH_MCR REG32 (ETH_BASE + 0x0000) +#define ETH_MAHR REG32 (ETH_BASE + 0x0004) +#define ETH_MALR REG32 (ETH_BASE + 0x0008) +#define ETH_HTHR REG32 (ETH_BASE + 0x000C) +#define ETH_HTLR REG32 (ETH_BASE + 0x0010) +#define ETH_MIAR REG32 (ETH_BASE + 0x0014) +#define ETH_MIDR REG32 (ETH_BASE + 0x0018) +#define ETH_FCR REG32 (ETH_BASE + 0x001C) +#define ETH_VTR1 REG32 (ETH_BASE + 0x0020) +#define ETH_VTR2 REG32 (ETH_BASE + 0x0024) +#define ETH_WKFR REG32 (ETH_BASE + 0x0028) +#define ETH_PMTR REG32 (ETH_BASE + 0x002C) + +/* Bus Mode Register (ETH_BMR) */ + +#define ETH_BMR_DBO (1 << 20) +#define ETH_BMR_PBL_BIT 8 +#define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) + #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) + #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) +#define ETH_BMR_BLE (1 << 7) +#define ETH_BMR_DSL_BIT 2 +#define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) + #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) + #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) + #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) + #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) + #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) +#define ETH_BMR_SWR (1 << 0) + +/* DMA Status Register (ETH_SR) */ + +#define ETH_SR_EB_BIT 23 +#define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) + #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) + #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) +#define ETH_SR_TS_BIT 20 +#define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) + #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) + #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) + #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) + #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) + #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) + #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) +#define ETH_SR_RS_BIT 17 +#define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) + #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) + #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) + #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) + #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) + #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) + #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) + #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) + #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) +#define ETH_SR_NIS (1 << 16) +#define ETH_SR_AIS (1 << 15) +#define ETH_SR_ERI (1 << 14) +#define ETH_SR_FBE (1 << 13) +#define ETH_SR_ETI (1 << 10) +#define ETH_SR_RWT (1 << 9) +#define ETH_SR_RPS (1 << 8) +#define ETH_SR_RU (1 << 7) +#define ETH_SR_RI (1 << 6) +#define ETH_SR_UNF (1 << 5) +#define ETH_SR_TJT (1 << 3) +#define ETH_SR_TU (1 << 2) +#define ETH_SR_TPS (1 << 1) +#define ETH_SR_TI (1 << 0) + +/* Control (Operation Mode) Register (ETH_CR) */ + +#define ETH_CR_TTM (1 << 22) +#define ETH_CR_SF (1 << 21) +#define ETH_CR_TR_BIT 14 +#define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) +#define ETH_CR_ST (1 << 13) +#define ETH_CR_OSF (1 << 2) +#define ETH_CR_SR (1 << 1) + +/* Interrupt Enable Register (ETH_IER) */ + +#define ETH_IER_NI (1 << 16) +#define ETH_IER_AI (1 << 15) +#define ETH_IER_ERE (1 << 14) +#define ETH_IER_FBE (1 << 13) +#define ETH_IER_ET (1 << 10) +#define ETH_IER_RWE (1 << 9) +#define ETH_IER_RS (1 << 8) +#define ETH_IER_RU (1 << 7) +#define ETH_IER_RI (1 << 6) +#define ETH_IER_UN (1 << 5) +#define ETH_IER_TJ (1 << 3) +#define ETH_IER_TU (1 << 2) +#define ETH_IER_TS (1 << 1) +#define ETH_IER_TI (1 << 0) + +/* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ + +#define ETH_MFCR_OVERFLOW_BIT 17 +#define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) +#define ETH_MFCR_MFC_BIT 0 +#define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) + +/* MAC Control Register (ETH_MCR) */ + +#define ETH_MCR_RA (1 << 31) +#define ETH_MCR_HBD (1 << 28) +#define ETH_MCR_PS (1 << 27) +#define ETH_MCR_DRO (1 << 23) +#define ETH_MCR_OM_BIT 21 +#define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) + #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) + #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) + #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) +#define ETH_MCR_F (1 << 20) +#define ETH_MCR_PM (1 << 19) +#define ETH_MCR_PR (1 << 18) +#define ETH_MCR_IF (1 << 17) +#define ETH_MCR_PB (1 << 16) +#define ETH_MCR_HO (1 << 15) +#define ETH_MCR_HP (1 << 13) +#define ETH_MCR_LCC (1 << 12) +#define ETH_MCR_DBF (1 << 11) +#define ETH_MCR_DTRY (1 << 10) +#define ETH_MCR_ASTP (1 << 8) +#define ETH_MCR_BOLMT_BIT 6 +#define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) + #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) + #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) + #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) + #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) +#define ETH_MCR_DC (1 << 5) +#define ETH_MCR_TE (1 << 3) +#define ETH_MCR_RE (1 << 2) + +/* MII Address Register (ETH_MIAR) */ + +#define ETH_MIAR_PHY_ADDR_BIT 11 +#define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) +#define ETH_MIAR_MII_BIT 6 +#define ETH_MIAR_MII_MASK (0x1f << ETH_MIAR_MII_BIT) +#define ETH_MIAR_MII_WRITE (1 << 1) +#define ETH_MIAR_MII_BUSY (1 << 0) + +/* Flow Control Register (ETH_FCR) */ + +#define ETH_FCR_PAUSE_TIME_BIT 16 +#define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) +#define ETH_FCR_PCF (1 << 2) +#define ETH_FCR_FCE (1 << 1) +#define ETH_FCR_BUSY (1 << 0) + +/* PMT Control and Status Register (ETH_PMTR) */ + +#define ETH_PMTR_GU (1 << 9) +#define ETH_PMTR_RF (1 << 6) +#define ETH_PMTR_MF (1 << 5) +#define ETH_PMTR_RWK (1 << 2) +#define ETH_PMTR_MPK (1 << 1) + +/* Receive Descriptor 0 (ETH_RD0) Bits */ + +#define ETH_RD0_OWN (1 << 31) +#define ETH_RD0_FF (1 << 30) +#define ETH_RD0_FL_BIT 16 +#define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) +#define ETH_RD0_ES (1 << 15) +#define ETH_RD0_DE (1 << 14) +#define ETH_RD0_LE (1 << 12) +#define ETH_RD0_RF (1 << 11) +#define ETH_RD0_MF (1 << 10) +#define ETH_RD0_FD (1 << 9) +#define ETH_RD0_LD (1 << 8) +#define ETH_RD0_TL (1 << 7) +#define ETH_RD0_CS (1 << 6) +#define ETH_RD0_FT (1 << 5) +#define ETH_RD0_WT (1 << 4) +#define ETH_RD0_ME (1 << 3) +#define ETH_RD0_DB (1 << 2) +#define ETH_RD0_CE (1 << 1) + +/* Receive Descriptor 1 (ETH_RD1) Bits */ + +#define ETH_RD1_RER (1 << 25) +#define ETH_RD1_RCH (1 << 24) +#define ETH_RD1_RBS2_BIT 11 +#define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) +#define ETH_RD1_RBS1_BIT 0 +#define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) + +/* Transmit Descriptor 0 (ETH_TD0) Bits */ + +#define ETH_TD0_OWN (1 << 31) +#define ETH_TD0_FA (1 << 15) +#define ETH_TD0_LOC (1 << 11) +#define ETH_TD0_NC (1 << 10) +#define ETH_TD0_LC (1 << 9) +#define ETH_TD0_EC (1 << 8) +#define ETH_TD0_HBF (1 << 7) +#define ETH_TD0_CC_BIT 3 +#define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) +#define ETH_TD0_ED (1 << 2) +#define ETH_TD0_UF (1 << 1) +#define ETH_TD0_DF (1 << 0) + +/* Transmit Descriptor 1 (ETH_TD1) Bits */ + +#define ETH_TD1_IC (1 << 31) +#define ETH_TD1_LS (1 << 30) +#define ETH_TD1_FS (1 << 29) +#define ETH_TD1_AC (1 << 26) +#define ETH_TD1_TER (1 << 25) +#define ETH_TD1_TCH (1 << 24) +#define ETH_TD1_DPD (1 << 23) +#define ETH_TD1_TBS2_BIT 11 +#define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) +#define ETH_TD1_TBS1_BIT 0 +#define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) + + + + +/************************************************************************* + * WDT + *************************************************************************/ +#define WDT_WTCSR REG8 (WDT_BASE + 0x00) +#define WDT_WTCNT REG32 (WDT_BASE + 0x04) + +#define WDT_WTCSR_START (1 << 4) + + + + +/************************************************************************* + * OST + *************************************************************************/ +#define OST_TER REG8 (OST_BASE + 0x00) +#define OST_TRDR(n) REG32 (OST_BASE + 0x10 + ((n) * 0x20)) +#define OST_TCNT(n) REG32 (OST_BASE + 0x14 + ((n) * 0x20)) +#define OST_TCSR(n) REG16 (OST_BASE + 0x18 + ((n) * 0x20)) +#define OST_TCRB(n) REG32 (OST_BASE + 0x1c + ((n) * 0x20)) + +#define OST_TCSR_BUSY (1 << 7) +#define OST_TCSR_UF (1 << 6) +#define OST_TCSR_UIE (1 << 5) +#define OST_TCSR_CKS_BIT 0 +#define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) + #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) + #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) + #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) + #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) + #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) + #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) + +#define OST_TCSR0 OST_TCSR(0) +#define OST_TCSR1 OST_TCSR(1) +#define OST_TCSR2 OST_TCSR(2) +#define OST_TRDR0 OST_TRDR(0) +#define OST_TRDR1 OST_TRDR(1) +#define OST_TRDR2 OST_TRDR(2) +#define OST_TCNT0 OST_TCNT(0) +#define OST_TCNT1 OST_TCNT(1) +#define OST_TCNT2 OST_TCNT(2) +#define OST_TCRB0 OST_TCRB(0) +#define OST_TCRB1 OST_TCRB(1) +#define OST_TCRB2 OST_TCRB(2) + +/************************************************************************* + * UART + *************************************************************************/ + +#define IRDA_BASE UART0_BASE +#define UART_BASE UART0_BASE +#define UART_OFF 0x1000 + +/* register offset */ +#define OFF_RDR (0x00) /* R 8b H'xx */ +#define OFF_TDR (0x00) /* W 8b H'xx */ +#define OFF_DLLR (0x00) /* RW 8b H'00 */ +#define OFF_DLHR (0x04) /* RW 8b H'00 */ +#define OFF_IER (0x04) /* RW 8b H'00 */ +#define OFF_ISR (0x08) /* R 8b H'01 */ +#define OFF_FCR (0x08) /* W 8b H'00 */ +#define OFF_LCR (0x0C) /* RW 8b H'00 */ +#define OFF_MCR (0x10) /* RW 8b H'00 */ +#define OFF_LSR (0x14) /* R 8b H'00 */ +#define OFF_MSR (0x18) /* R 8b H'00 */ +#define OFF_SPR (0x1C) /* RW 8b H'00 */ +#define OFF_MCR (0x10) /* RW 8b H'00 */ +#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ + +/* register address */ +#define UART0_RDR REG32 (UART0_BASE + OFF_RDR) +#define UART0_TDR REG32 (UART0_BASE + OFF_TDR) +#define UART0_DLLR REG32 (UART0_BASE + OFF_DLLR) +#define UART0_DLHR REG32 (UART0_BASE + OFF_DLHR) +#define UART0_IER REG32 (UART0_BASE + OFF_IER) +#define UART0_ISR REG32 (UART0_BASE + OFF_ISR) +#define UART0_FCR REG32 (UART0_BASE + OFF_FCR) +#define UART0_LCR REG32 (UART0_BASE + OFF_LCR) +#define UART0_MCR REG32 (UART0_BASE + OFF_MCR) +#define UART0_LSR REG32 (UART0_BASE + OFF_LSR) +#define UART0_MSR REG32 (UART0_BASE + OFF_MSR) +#define UART0_SPR REG32 (UART0_BASE + OFF_SPR) +#define UART0_SIRCR REG32 (UART0_BASE + OFF_SIRCR) + +#define UART1_RDR REG32 (UART1_BASE + OFF_RDR) +#define UART1_TDR REG32 (UART1_BASE + OFF_TDR) +#define UART1_DLLR REG32 (UART1_BASE + OFF_DLLR) +#define UART1_DLHR REG32 (UART1_BASE + OFF_DLHR) +#define UART1_IER REG32 (UART1_BASE + OFF_IER) +#define UART1_ISR REG32 (UART1_BASE + OFF_ISR) +#define UART1_FCR REG32 (UART1_BASE + OFF_FCR) +#define UART1_LCR REG32 (UART1_BASE + OFF_LCR) +#define UART1_MCR REG32 (UART1_BASE + OFF_MCR) +#define UART1_LSR REG32 (UART1_BASE + OFF_LSR) +#define UART1_MSR REG32 (UART1_BASE + OFF_MSR) +#define UART1_SPR REG32 (UART1_BASE + OFF_SPR) +#define UART1_SIRCR REG32 (UART1_BASE + OFF_SIRCR) + +#define UART2_RDR REG32 (UART2_BASE + OFF_RDR) +#define UART2_TDR REG32 (UART2_BASE + OFF_TDR) +#define UART2_DLLR REG32 (UART2_BASE + OFF_DLLR) +#define UART2_DLHR REG32 (UART2_BASE + OFF_DLHR) +#define UART2_IER REG32 (UART2_BASE + OFF_IER) +#define UART2_ISR REG32 (UART2_BASE + OFF_ISR) +#define UART2_FCR REG32 (UART2_BASE + OFF_FCR) +#define UART2_LCR REG32 (UART2_BASE + OFF_LCR) +#define UART2_MCR REG32 (UART2_BASE + OFF_MCR) +#define UART2_LSR REG32 (UART2_BASE + OFF_LSR) +#define UART2_MSR REG32 (UART2_BASE + OFF_MSR) +#define UART2_SPR REG32 (UART2_BASE + OFF_SPR) +#define UART2_SIRCR REG32 (UART2_BASE + OFF_SIRCR) + +#define UART3_RDR REG32 (UART3_BASE + OFF_RDR) +#define UART3_TDR REG32 (UART3_BASE + OFF_TDR) +#define UART3_DLLR REG32 (UART3_BASE + OFF_DLLR) +#define UART3_DLHR REG32 (UART3_BASE + OFF_DLHR) +#define UART3_IER REG32 (UART3_BASE + OFF_IER) +#define UART3_ISR REG32 (UART3_BASE + OFF_ISR) +#define UART3_FCR REG32 (UART3_BASE + OFF_FCR) +#define UART3_LCR REG32 (UART3_BASE + OFF_LCR) +#define UART3_MCR REG32 (UART3_BASE + OFF_MCR) +#define UART3_LSR REG32 (UART3_BASE + OFF_LSR) +#define UART3_MSR REG32 (UART3_BASE + OFF_MSR) +#define UART3_SPR REG32 (UART3_BASE + OFF_SPR) +#define UART3_SIRCR REG32 (UART3_BASE + OFF_SIRCR) + +/* + * Define macros for UARTIER + * UART Interrupt Enable Register + */ +#define UARTIER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ +#define UARTIER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ +#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ +#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */ +#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ + +/* + * Define macros for UARTISR + * UART Interrupt Status Register + */ +#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ +#define UARTISR_IID (7 << 1) /* Source of Interrupt */ +#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */ +#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ +#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */ +#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ +#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */ +#define UARTISR_FFMS_NO_FIFO (0 << 6) +#define UARTISR_FFMS_FIFO_MODE (3 << 6) + +/* + * Define macros for UARTFCR + * UART FIFO Control Register + */ +#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ +#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ +#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ +#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */ +#define UARTFCR_UUE (1 << 4) /* 0: disable UART */ +#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ +#define UARTFCR_RTRG_1 (0 << 6) +#define UARTFCR_RTRG_4 (1 << 6) +#define UARTFCR_RTRG_8 (2 << 6) +#define UARTFCR_RTRG_15 (3 << 6) + +/* + * Define macros for UARTLCR + * UART Line Control Register + */ +#define UARTLCR_WLEN (3 << 0) /* word length */ +#define UARTLCR_WLEN_5 (0 << 0) +#define UARTLCR_WLEN_6 (1 << 0) +#define UARTLCR_WLEN_7 (2 << 0) +#define UARTLCR_WLEN_8 (3 << 0) +#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ +#define UARTLCR_PE (1 << 3) /* 0: parity disable */ +#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ +#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */ +#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ +#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */ + +/* + * Define macros for UARTLSR + * UART Line Status Register + */ +#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ +#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */ +#define UARTLSR_PER (1 << 2) /* 0: no parity error */ +#define UARTLSR_FER (1 << 3) /* 0; no framing error */ +#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ +#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ +#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ +#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ + +/* + * Define macros for UARTMCR + * UART Modem Control Register + */ +#define UARTMCR_DTR (1 << 0) /* 0: DTR_ ouput high */ +#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high */ +#define UARTMCR_OUT1 (1 << 2) /* 0: UARTMSR.RI is set to 0 and RI_ input high */ +#define UARTMCR_OUT2 (1 << 3) /* 0: UARTMSR.DCD is set to 0 and DCD_ input high */ +#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ +#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */ + +/* + * Define macros for UARTMSR + * UART Modem Status Register + */ +#define UARTMSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UARTMSR */ +#define UARTMSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UARTMSR */ +#define UARTMSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UARTMSR */ +#define UARTMSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UARTMSR */ +#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */ +#define UARTMSR_DSR (1 << 5) /* 0: DSR_ pin is high */ +#define UARTMSR_RI (1 << 6) /* 0: RI_ pin is high */ +#define UARTMSR_DCD (1 << 7) /* 0: DCD_ pin is high */ + +/* + * Define macros for SIRCR + * Slow IrDA Control Register + */ +#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ +#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ +#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length + 1: 0 pulse width is 1.6us for 115.2Kbps */ +#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ +#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ + + + +/************************************************************************* + * INTC + *************************************************************************/ +#define INTC_ISR REG32 (INTC_BASE + 0x00) +#define INTC_IMR REG32 (INTC_BASE + 0x04) +#define INTC_IMSR REG32 (INTC_BASE + 0x08) +#define INTC_IMCR REG32 (INTC_BASE + 0x0c) +#define INTC_IPR REG32 (INTC_BASE + 0x10) + +#define IRQ_I2C 1 +#define IRQ_PS2 2 +#define IRQ_UPRT 3 +#define IRQ_CORE 4 +#define IRQ_UART3 6 +#define IRQ_UART2 7 +#define IRQ_UART1 8 +#define IRQ_UART0 9 +#define IRQ_SCC1 10 +#define IRQ_SCC0 11 +#define IRQ_UDC 12 +#define IRQ_UHC 13 +#define IRQ_MSC 14 +#define IRQ_RTC 15 +#define IRQ_FIR 16 +#define IRQ_SSI 17 +#define IRQ_CIM 18 +#define IRQ_ETH 19 +#define IRQ_AIC 20 +#define IRQ_DMAC 21 +#define IRQ_OST2 22 +#define IRQ_OST1 23 +#define IRQ_OST0 24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_LCD 30 + + + + +/************************************************************************* + * CIM + *************************************************************************/ +#define CIM_CFG REG32 (CIM_BASE + 0x0000) +#define CIM_CTRL REG32 (CIM_BASE + 0x0004) +#define CIM_STATE REG32 (CIM_BASE + 0x0008) +#define CIM_IID REG32 (CIM_BASE + 0x000C) +#define CIM_RXFIFO REG32 (CIM_BASE + 0x0010) +#define CIM_DA REG32 (CIM_BASE + 0x0020) +#define CIM_FA REG32 (CIM_BASE + 0x0024) +#define CIM_FID REG32 (CIM_BASE + 0x0028) +#define CIM_CMD REG32 (CIM_BASE + 0x002C) + +/* CIM Configuration Register (CIM_CFG) */ + +#define CIM_CFG_INV_DAT (1 << 15) +#define CIM_CFG_VSP (1 << 14) +#define CIM_CFG_HSP (1 << 13) +#define CIM_CFG_PCP (1 << 12) +#define CIM_CFG_DUMMY_ZERO (1 << 9) +#define CIM_CFG_EXT_VSYNC (1 << 8) +#define CIM_CFG_PACK_BIT 4 +#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) + #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) +#define CIM_CFG_DSM_BIT 0 +#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) + #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ + #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ + #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ + #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ + +/* CIM Control Register (CIM_CTRL) */ + +#define CIM_CTRL_MCLKDIV_BIT 24 +#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) +#define CIM_CTRL_FRC_BIT 16 +#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) + #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ + #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ + #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ + #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ + #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ + #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ + #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ + #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ + #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ + #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ + #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ + #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ + #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ + #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ + #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ + #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ +#define CIM_CTRL_VDDM (1 << 13) +#define CIM_CTRL_DMA_SOFM (1 << 12) +#define CIM_CTRL_DMA_EOFM (1 << 11) +#define CIM_CTRL_DMA_STOPM (1 << 10) +#define CIM_CTRL_RXF_TRIGM (1 << 9) +#define CIM_CTRL_RXF_OFM (1 << 8) +#define CIM_CTRL_RXF_TRIG_BIT 4 +#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) + #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ + #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ + #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ + #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ + #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ + #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ + #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ + #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ +#define CIM_CTRL_DMA_EN (1 << 2) +#define CIM_CTRL_RXF_RST (1 << 1) +#define CIM_CTRL_ENA (1 << 0) + +/* CIM State Register (CIM_STATE) */ + +#define CIM_STATE_DMA_SOF (1 << 6) +#define CIM_STATE_DMA_EOF (1 << 5) +#define CIM_STATE_DMA_STOP (1 << 4) +#define CIM_STATE_RXF_OF (1 << 3) +#define CIM_STATE_RXF_TRIG (1 << 2) +#define CIM_STATE_RXF_EMPTY (1 << 1) +#define CIM_STATE_VDD (1 << 0) + +/* CIM DMA Command Register (CIM_CMD) */ + +#define CIM_CMD_SOFINT (1 << 31) +#define CIM_CMD_EOFINT (1 << 30) +#define CIM_CMD_STOP (1 << 28) +#define CIM_CMD_LEN_BIT 0 +#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) + + + + +/************************************************************************* + * PWM + *************************************************************************/ +#define PWM_CTR(n) REG8 (PWM##n##_BASE + 0x000) +#define PWM_PER(n) REG16 (PWM##n##_BASE + 0x004) +#define PWM_DUT(n) REG16 (PWM##n##_BASE + 0x008) + +/* PWM Control Register (PWM_CTR) */ + +#define PWM_CTR_EN (1 << 7) +#define PWM_CTR_SD (1 << 6) +#define PWM_CTR_PRESCALE_BIT 0 +#define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) + +/* PWM Period Register (PWM_PER) */ + +#define PWM_PER_PERIOD_BIT 0 +#define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) + +/* PWM Duty Register (PWM_DUT) */ + +#define PWM_DUT_FDUTY (1 << 10) +#define PWM_DUT_DUTY_BIT 0 +#define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) + + + + +/************************************************************************* + * EMC + *************************************************************************/ +#define EMC_BCR REG32 (EMC_BASE + 0x00) +#define EMC_SMCR0 REG32 (EMC_BASE + 0x10) +#define EMC_SMCR1 REG32 (EMC_BASE + 0x14) +#define EMC_SMCR2 REG32 (EMC_BASE + 0x18) +#define EMC_SMCR3 REG32 (EMC_BASE + 0x1c) +#define EMC_SMCR4 REG32 (EMC_BASE + 0x20) +#define EMC_SMCR5 REG32 (EMC_BASE + 0x24) +#define EMC_SMCR6 REG32 (EMC_BASE + 0x28) +#define EMC_SMCR7 REG32 (EMC_BASE + 0x2c) +#define EMC_SACR0 REG32 (EMC_BASE + 0x30) +#define EMC_SACR1 REG32 (EMC_BASE + 0x34) +#define EMC_SACR2 REG32 (EMC_BASE + 0x38) +#define EMC_SACR3 REG32 (EMC_BASE + 0x3c) +#define EMC_SACR4 REG32 (EMC_BASE + 0x40) +#define EMC_SACR5 REG32 (EMC_BASE + 0x44) +#define EMC_SACR6 REG32 (EMC_BASE + 0x48) +#define EMC_SACR7 REG32 (EMC_BASE + 0x4c) +#define EMC_NFCSR REG32 (EMC_BASE + 0x50) +#define EMC_NFECC REG32 (EMC_BASE + 0x54) +#define EMC_PCCR1 REG32 (EMC_BASE + 0x60) +#define EMC_PCCR2 REG32 (EMC_BASE + 0x64) +#define EMC_PCCR3 REG32 (EMC_BASE + 0x68) +#define EMC_PCCR4 REG32 (EMC_BASE + 0x6c) +#define EMC_DMCR REG32 (EMC_BASE + 0x80) +#define EMC_RTCSR REG32 (EMC_BASE + 0x84) +#define EMC_RTCNT REG32 (EMC_BASE + 0x88) +#define EMC_RTCOR REG32 (EMC_BASE + 0x8c) +#define EMC_DMAR1 REG32 (EMC_BASE + 0x90) +#define EMC_DMAR2 REG32 (EMC_BASE + 0x94) +#define EMC_DMAR3 REG32 (EMC_BASE + 0x98) +#define EMC_DMAR4 REG32 (EMC_BASE + 0x9c) + +#define EMC_SDMR0 REG32 (EMC_BASE + 0xa000) +#define EMC_SDMR1 REG32 (EMC_BASE + 0xb000) +#define EMC_SDMR2 REG32 (EMC_BASE + 0xc000) +#define EMC_SDMR3 REG32 (EMC_BASE + 0xd000) + + +#define EMC_BCR_BRE (1 << 1) + +#define EMC_SMCR_STRV_BIT 24 +#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) +#define EMC_SMCR_TAW_BIT 20 +#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) +#define EMC_SMCR_TBP_BIT 16 +#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) +#define EMC_SMCR_TAH_BIT 12 +#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) +#define EMC_SMCR_TAS_BIT 8 +#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) +#define EMC_SMCR_BW_BIT 6 +#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) + #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) + #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) + #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) +#define EMC_SMCR_BCM (1 << 3) +#define EMC_SMCR_BL_BIT 1 +#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) + #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_SMT (1 << 0) + +#define EMC_SACR_BASE_BIT 8 +#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) +#define EMC_SACR_MASK_BIT 0 +#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) + +#define EMC_NFCSR_RB (1 << 7) +#define EMC_NFCSR_BOOT_SEL_BIT 4 +#define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) +#define EMC_NFCSR_ERST (1 << 3) +#define EMC_NFCSR_ECCE (1 << 2) +#define EMC_NFCSR_FCE (1 << 1) +#define EMC_NFCSR_NFE (1 << 0) + +#define EMC_NFECC_ECC2_BIT 16 +#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) +#define EMC_NFECC_ECC1_BIT 8 +#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) +#define EMC_NFECC_ECC0_BIT 0 +#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) + +#define EMC_DMCR_BW_BIT 31 +#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) +#define EMC_DMCR_CA_BIT 26 +#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) + #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_RMODE (1 << 25) +#define EMC_DMCR_RFSH (1 << 24) +#define EMC_DMCR_MRSET (1 << 23) +#define EMC_DMCR_RA_BIT 20 +#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) + #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) + #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) + #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) +#define EMC_DMCR_BA_BIT 19 +#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) +#define EMC_DMCR_PDM (1 << 18) +#define EMC_DMCR_EPIN (1 << 17) +#define EMC_DMCR_TRAS_BIT 13 +#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) +#define EMC_DMCR_RCD_BIT 11 +#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) +#define EMC_DMCR_TPC_BIT 8 +#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) +#define EMC_DMCR_TRWL_BIT 5 +#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) +#define EMC_DMCR_TRC_BIT 2 +#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) +#define EMC_DMCR_TCL_BIT 0 +#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) + +#define EMC_RTCSR_CMF (1 << 7) +#define EMC_RTCSR_CKS_BIT 0 +#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) + #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) + +#define EMC_DMAR_BASE_BIT 8 +#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) +#define EMC_DMAR_MASK_BIT 0 +#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) + +#define EMC_SDMR_BM (1 << 9) +#define EMC_SDMR_OM_BIT 7 +#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) + #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) +#define EMC_SDMR_CAS_BIT 4 +#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) + #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) + #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) + #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) +#define EMC_SDMR_BT_BIT 3 +#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) + #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) + #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) +#define EMC_SDMR_BL_BIT 0 +#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) + #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) + +#define EMC_SDMR_CAS2_16BIT (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) +#define EMC_SDMR_CAS2_32BIT (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) +#define EMC_SDMR_CAS3_16BIT (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) +#define EMC_SDMR_CAS3_32BIT (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) + +#define EMC_PCCR12_AMW (1 << 31) +#define EMC_PCCR12_AMAS_BIT 28 +#define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) +#define EMC_PCCR12_AMAH_BIT 24 +#define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) +#define EMC_PCCR12_AMPW_BIT 20 +#define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) +#define EMC_PCCR12_AMRT_BIT 16 +#define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) +#define EMC_PCCR12_CMW (1 << 15) +#define EMC_PCCR12_CMAS_BIT 12 +#define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) +#define EMC_PCCR12_CMAH_BIT 8 +#define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) +#define EMC_PCCR12_CMPW_BIT 4 +#define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) +#define EMC_PCCR12_CMRT_BIT 0 +#define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) + +#define EMC_PCCR34_DRS_BIT 16 +#define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) + #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) + #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) + #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) +#define EMC_PCCR34_IOIS16 (1 << 15) +#define EMC_PCCR34_IOW (1 << 14) +#define EMC_PCCR34_TCB_BIT 12 +#define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) +#define EMC_PCCR34_IORT_BIT 8 +#define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) +#define EMC_PCCR34_IOAE_BIT 6 +#define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) + #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) + #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) + #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) + #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) +#define EMC_PCCR34_IOAH_BIT 4 +#define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) + #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) + #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) + #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) + #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) +#define EMC_PCCR34_IOPW_BIT 0 +#define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) + + + + +/************************************************************************* + * GPIO + *************************************************************************/ +#define GPIO_GPDR(n) REG32 (GPIO_BASE + (0x00 + (n)*0x30)) +#define GPIO_GPDIR(n) REG32 (GPIO_BASE + (0x04 + (n)*0x30)) +#define GPIO_GPODR(n) REG32 (GPIO_BASE + (0x08 + (n)*0x30)) +#define GPIO_GPPUR(n) REG32 (GPIO_BASE + (0x0c + (n)*0x30)) +#define GPIO_GPALR(n) REG32 (GPIO_BASE + (0x10 + (n)*0x30)) +#define GPIO_GPAUR(n) REG32 (GPIO_BASE + (0x14 + (n)*0x30)) +#define GPIO_GPIDLR(n) REG32 (GPIO_BASE + (0x18 + (n)*0x30)) +#define GPIO_GPIDUR(n) REG32 (GPIO_BASE + (0x1c + (n)*0x30)) +#define GPIO_GPIER(n) REG32 (GPIO_BASE + (0x20 + (n)*0x30)) +#define GPIO_GPIMR(n) REG32 (GPIO_BASE + (0x24 + (n)*0x30)) +#define GPIO_GPFR(n) REG32 (GPIO_BASE + (0x28 + (n)*0x30)) + +#define GPIO_IRQ_LOLEVEL 0 +#define GPIO_IRQ_HILEVEL 1 +#define GPIO_IRQ_FALLEDG 2 +#define GPIO_IRQ_RAISEDG 3 + +#define IRQ_GPIO_0 48 +#define NUM_GPIO 128 + + +/************************************************************************* + * HARB + *************************************************************************/ +#define HARB_HAPOR REG32 (HARB_BASE + 0x000) +#define HARB_HMCTR REG32 (HARB_BASE + 0x010) +#define HARB_HME8H REG32 (HARB_BASE + 0x014) +#define HARB_HMCR1 REG32 (HARB_BASE + 0x018) +#define HARB_HMER2 REG32 (HARB_BASE + 0x01C) +#define HARB_HMER3 REG32 (HARB_BASE + 0x020) +#define HARB_HMLTR REG32 (HARB_BASE + 0x024) + +/* HARB Priority Order Register (HARB_HAPOR) */ + +#define HARB_HAPOR_UCHSEL (1 << 7) +#define HARB_HAPOR_PRIO_BIT 0 +#define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) + +/* AHB Monitor Control Register (HARB_HMCTR) */ + +#define HARB_HMCTR_HET3_BIT 20 +#define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) +#define HARB_HMCTR_HMS3_BIT 16 +#define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) +#define HARB_HMCTR_HET2_BIT 12 +#define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) +#define HARB_HMCTR_HMS2_BIT 8 +#define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) +#define HARB_HMCTR_HOVF3 (1 << 7) +#define HARB_HMCTR_HOVF2 (1 << 6) +#define HARB_HMCTR_HOVF1 (1 << 5) +#define HARB_HMCTR_HRST (1 << 4) +#define HARB_HMCTR_HEE3 (1 << 2) +#define HARB_HMCTR_HEE2 (1 << 1) +#define HARB_HMCTR_HEE1 (1 << 0) + +/* AHB Monitor Event 8bits High Register (HARB_HME8H) */ + +#define HARB_HME8H_HC8H1_BIT 16 +#define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) +#define HARB_HME8H_HC8H2_BIT 8 +#define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) +#define HARB_HME8H_HC8H3_BIT 0 +#define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) + +/* AHB Monitor Latency Register (HARB_HMLTR) */ + +#define HARB_HMLTR_HLT2_BIT 16 +#define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) +#define HARB_HMLTR_HLT3_BIT 0 +#define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) + + + + +/************************************************************************* + * I2C + *************************************************************************/ +#define I2C_DR REG8 (I2C_BASE + 0x000) +#define I2C_CR REG8 (I2C_BASE + 0x004) +#define I2C_SR REG8 (I2C_BASE + 0x008) +#define I2C_GR REG16 (I2C_BASE + 0x00C) + +/* I2C Control Register (I2C_CR) */ + +#define I2C_CR_IEN (1 << 4) +#define I2C_CR_STA (1 << 3) +#define I2C_CR_STO (1 << 2) +#define I2C_CR_AC (1 << 1) +#define I2C_CR_I2CE (1 << 0) + +/* I2C Status Register (I2C_SR) */ + +#define I2C_SR_STX (1 << 4) +#define I2C_SR_BUSY (1 << 3) +#define I2C_SR_TEND (1 << 2) +#define I2C_SR_DRF (1 << 1) +#define I2C_SR_ACKF (1 << 0) + + + + +/************************************************************************* + * UDC + *************************************************************************/ +#define UDC_EP0InCR REG32 (UDC_BASE + 0x00) +#define UDC_EP0InSR REG32 (UDC_BASE + 0x04) +#define UDC_EP0InBSR REG32 (UDC_BASE + 0x08) +#define UDC_EP0InMPSR REG32 (UDC_BASE + 0x0c) +#define UDC_EP0InDesR REG32 (UDC_BASE + 0x14) +#define UDC_EP1InCR REG32 (UDC_BASE + 0x20) +#define UDC_EP1InSR REG32 (UDC_BASE + 0x24) +#define UDC_EP1InBSR REG32 (UDC_BASE + 0x28) +#define UDC_EP1InMPSR REG32 (UDC_BASE + 0x2c) +#define UDC_EP1InDesR REG32 (UDC_BASE + 0x34) +#define UDC_EP2InCR REG32 (UDC_BASE + 0x40) +#define UDC_EP2InSR REG32 (UDC_BASE + 0x44) +#define UDC_EP2InBSR REG32 (UDC_BASE + 0x48) +#define UDC_EP2InMPSR REG32 (UDC_BASE + 0x4c) +#define UDC_EP2InDesR REG32 (UDC_BASE + 0x54) +#define UDC_EP3InCR REG32 (UDC_BASE + 0x60) +#define UDC_EP3InSR REG32 (UDC_BASE + 0x64) +#define UDC_EP3InBSR REG32 (UDC_BASE + 0x68) +#define UDC_EP3InMPSR REG32 (UDC_BASE + 0x6c) +#define UDC_EP3InDesR REG32 (UDC_BASE + 0x74) +#define UDC_EP4InCR REG32 (UDC_BASE + 0x80) +#define UDC_EP4InSR REG32 (UDC_BASE + 0x84) +#define UDC_EP4InBSR REG32 (UDC_BASE + 0x88) +#define UDC_EP4InMPSR REG32 (UDC_BASE + 0x8c) +#define UDC_EP4InDesR REG32 (UDC_BASE + 0x94) + +#define UDC_EP0OutCR REG32 (UDC_BASE + 0x200) +#define UDC_EP0OutSR REG32 (UDC_BASE + 0x204) +#define UDC_EP0OutPFNR REG32 (UDC_BASE + 0x208) +#define UDC_EP0OutMPSR REG32 (UDC_BASE + 0x20c) +#define UDC_EP0OutSBPR REG32 (UDC_BASE + 0x210) +#define UDC_EP0OutDesR REG32 (UDC_BASE + 0x214) +#define UDC_EP5OutCR REG32 (UDC_BASE + 0x2a0) +#define UDC_EP5OutSR REG32 (UDC_BASE + 0x2a4) +#define UDC_EP5OutPFNR REG32 (UDC_BASE + 0x2a8) +#define UDC_EP5OutMPSR REG32 (UDC_BASE + 0x2ac) +#define UDC_EP5OutDesR REG32 (UDC_BASE + 0x2b4) +#define UDC_EP6OutCR REG32 (UDC_BASE + 0x2c0) +#define UDC_EP6OutSR REG32 (UDC_BASE + 0x2c4) +#define UDC_EP6OutPFNR REG32 (UDC_BASE + 0x2c8) +#define UDC_EP6OutMPSR REG32 (UDC_BASE + 0x2cc) +#define UDC_EP6OutDesR REG32 (UDC_BASE + 0x2d4) +#define UDC_EP7OutCR REG32 (UDC_BASE + 0x2e0) +#define UDC_EP7OutSR REG32 (UDC_BASE + 0x2e4) +#define UDC_EP7OutPFNR REG32 (UDC_BASE + 0x2e8) +#define UDC_EP7OutMPSR REG32 (UDC_BASE + 0x2ec) +#define UDC_EP7OutDesR REG32 (UDC_BASE + 0x2f4) + +#define UDC_DevCFGR REG32 (UDC_BASE + 0x400) +#define UDC_DevCR REG32 (UDC_BASE + 0x404) +#define UDC_DevSR REG32 (UDC_BASE + 0x408) +#define UDC_DevIntR REG32 (UDC_BASE + 0x40c) +#define UDC_DevIntMR REG32 (UDC_BASE + 0x410) +#define UDC_EPIntR REG32 (UDC_BASE + 0x414) +#define UDC_EPIntMR REG32 (UDC_BASE + 0x418) + +#define UDC_STCMAR REG32 (UDC_BASE + 0x500) +#define UDC_EP0InfR REG32 (UDC_BASE + 0x504) +#define UDC_EP1InfR REG32 (UDC_BASE + 0x508) +#define UDC_EP2InfR REG32 (UDC_BASE + 0x50c) +#define UDC_EP3InfR REG32 (UDC_BASE + 0x510) +#define UDC_EP4InfR REG32 (UDC_BASE + 0x514) +#define UDC_EP5InfR REG32 (UDC_BASE + 0x518) +#define UDC_EP6InfR REG32 (UDC_BASE + 0x51c) +#define UDC_EP7InfR REG32 (UDC_BASE + 0x520) + +#define UDC_TXCONFIRM REG32 (UDC_BASE + 0x41C) +#define UDC_TXZLP REG32 (UDC_BASE + 0x420) +#define UDC_RXCONFIRM REG32 (UDC_BASE + 0x41C) + +#define UDC_RXFIFO REG32 (UDC_BASE + 0x800) +#define UDC_TXFIFOEP0 REG32 (UDC_BASE + 0x840) + +#define UDC_DevCFGR_PI (1 << 5) +#define UDC_DevCFGR_SS (1 << 4) +#define UDC_DevCFGR_SP (1 << 3) +#define UDC_DevCFGR_RW (1 << 2) +#define UDC_DevCFGR_SPD_BIT 0 +#define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) + #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) + #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) + #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) + +#define UDC_DevCR_DM (1 << 9) +#define UDC_DevCR_BE (1 << 5) +#define UDC_DevCR_RES (1 << 0) + +#define UDC_DevSR_ENUMSPD_BIT 13 +#define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) + #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) + #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) + #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) +#define UDC_DevSR_SUSP (1 << 12) +#define UDC_DevSR_ALT_BIT 8 +#define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) +#define UDC_DevSR_INTF_BIT 4 +#define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) +#define UDC_DevSR_CFG_BIT 0 +#define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) + +#define UDC_DevIntR_ENUM (1 << 6) +#define UDC_DevIntR_SOF (1 << 5) +#define UDC_DevIntR_US (1 << 4) +#define UDC_DevIntR_UR (1 << 3) +#define UDC_DevIntR_SI (1 << 1) +#define UDC_DevIntR_SC (1 << 0) + +#define UDC_EPIntR_OUTEP_BIT 16 +#define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) +#define UDC_EPIntR_OUTEP0 0x00010000 +#define UDC_EPIntR_OUTEP5 0x00200000 +#define UDC_EPIntR_OUTEP6 0x00400000 +#define UDC_EPIntR_OUTEP7 0x00800000 +#define UDC_EPIntR_INEP_BIT 0 +#define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) +#define UDC_EPIntR_INEP0 0x00000001 +#define UDC_EPIntR_INEP1 0x00000002 +#define UDC_EPIntR_INEP2 0x00000004 +#define UDC_EPIntR_INEP3 0x00000008 +#define UDC_EPIntR_INEP4 0x00000010 + + +#define UDC_EPIntMR_OUTEP_BIT 16 +#define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) +#define UDC_EPIntMR_INEP_BIT 0 +#define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) + +#define UDC_EPCR_ET_BIT 4 +#define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) + #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) + #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) + #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) + #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) +#define UDC_EPCR_SN (1 << 2) +#define UDC_EPCR_F (1 << 1) +#define UDC_EPCR_S (1 << 0) + +#define UDC_EPSR_RXPKTSIZE_BIT 11 +#define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) +#define UDC_EPSR_IN (1 << 6) +#define UDC_EPSR_OUT_BIT 4 +#define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) + #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) + #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) + #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) +#define UDC_EPSR_PID_BIT 0 +#define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) + +#define UDC_EPInfR_MPS_BIT 19 +#define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) +#define UDC_EPInfR_ALTS_BIT 15 +#define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) +#define UDC_EPInfR_IFN_BIT 11 +#define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) +#define UDC_EPInfR_CGN_BIT 7 +#define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) +#define UDC_EPInfR_EPT_BIT 5 +#define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) + #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) + #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) + #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) + #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) +#define UDC_EPInfR_EPD (1 << 4) + #define UDC_EPInfR_EPD_OUT (0 << 4) + #define UDC_EPInfR_EPD_IN (1 << 4) + +#define UDC_EPInfR_EPN_BIT 0 +#define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) + + + + +/************************************************************************* + * DMAC + *************************************************************************/ +#define DMAC_DSAR(n) REG32 (DMAC_BASE + (0x00 + (n) * 0x20)) +#define DMAC_DDAR(n) REG32 (DMAC_BASE + (0x04 + (n) * 0x20)) +#define DMAC_DTCR(n) REG32 (DMAC_BASE + (0x08 + (n) * 0x20)) +#define DMAC_DRSR(n) REG32 (DMAC_BASE + (0x0c + (n) * 0x20)) +#define DMAC_DCCSR(n) REG32 (DMAC_BASE + (0x10 + (n) * 0x20)) +#define DMAC_DMAIPR REG32 (DMAC_BASE + 0xf8) +#define DMAC_DMACR REG32 (DMAC_BASE + 0xfc) + +#define DMAC_DRSR_RS_BIT 0 +#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) + #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) + +#define DMAC_DCCSR_EACKS (1 << 31) +#define DMAC_DCCSR_EACKM (1 << 30) +#define DMAC_DCCSR_ERDM_BIT 28 +#define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) + #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) + #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) + #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) + #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) +#define DMAC_DCCSR_EOPM (1 << 27) +#define DMAC_DCCSR_SAM (1 << 23) +#define DMAC_DCCSR_DAM (1 << 22) +#define DMAC_DCCSR_RDIL_BIT 16 +#define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) + #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) +#define DMAC_DCCSR_SWDH_BIT 14 +#define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) + #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) + #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) + #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) +#define DMAC_DCCSR_DWDH_BIT 12 +#define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) + #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) + #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) + #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) +#define DMAC_DCCSR_DS_BIT 8 +#define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) + #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) + #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) + #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) + #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) + #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) +#define DMAC_DCCSR_TM (1 << 7) +#define DMAC_DCCSR_AR (1 << 4) +#define DMAC_DCCSR_TC (1 << 3) +#define DMAC_DCCSR_HLT (1 << 2) +#define DMAC_DCCSR_TCIE (1 << 1) +#define DMAC_DCCSR_CHDE (1 << 0) + +#define DMAC_DMAIPR_CINT_BIT 8 +#define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) + +#define DMAC_DMACR_PR_BIT 8 +#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) + #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) +#define DMAC_DMACR_HTR (1 << 3) +#define DMAC_DMACR_AER (1 << 2) +#define DMAC_DMACR_DME (1 << 0) + +#define IRQ_DMA_0 32 +#define NUM_DMA 6 + +#define DMAC_DSAR0 DMAC_DSAR(0) +#define DMAC_DDAR0 DMAC_DDAR(0) +#define DMAC_DTCR0 DMAC_DTCR(0) +#define DMAC_DRSR0 DMAC_DRSR(0) +#define DMAC_DCCSR0 DMAC_DCCSR(0) + +#define DMAC_DSAR1 DMAC_DSAR(1) +#define DMAC_DDAR1 DMAC_DDAR(1) +#define DMAC_DTCR1 DMAC_DTCR(1) +#define DMAC_DRSR1 DMAC_DRSR(1) +#define DMAC_DCCSR1 DMAC_DCCSR(1) + +#define DMAC_DSAR2 DMAC_DSAR(2) +#define DMAC_DDAR2 DMAC_DDAR(2) +#define DMAC_DTCR2 DMAC_DTCR(2) +#define DMAC_DRSR2 DMAC_DRSR(2) +#define DMAC_DCCSR2 DMAC_DCCSR(2) + +#define DMAC_DSAR3 DMAC_DSAR(3) +#define DMAC_DDAR3 DMAC_DDAR(3) +#define DMAC_DTCR3 DMAC_DTCR(3) +#define DMAC_DRSR3 DMAC_DRSR(3) +#define DMAC_DCCSR3 DMAC_DCCSR(3) + +#define DMAC_DSAR4 DMAC_DSAR(4) +#define DMAC_DDAR4 DMAC_DDAR(4) +#define DMAC_DTCR4 DMAC_DTCR(4) +#define DMAC_DRSR4 DMAC_DRSR(4) +#define DMAC_DCCSR4 DMAC_DCCSR(4) + +#define DMAC_DSAR5 DMAC_DSAR(5) +#define DMAC_DDAR5 DMAC_DDAR(5) +#define DMAC_DTCR5 DMAC_DTCR(5) +#define DMAC_DRSR5 DMAC_DRSR(5) +#define DMAC_DCCSR5 DMAC_DCCSR(5) + +#define DMAC_DSAR6 DMAC_DSAR(6) +#define DMAC_DDAR6 DMAC_DDAR(6) +#define DMAC_DTCR6 DMAC_DTCR(6) +#define DMAC_DRSR6 DMAC_DRSR(6) +#define DMAC_DCCSR6 DMAC_DCCSR(6) + +#define DMAC_DSAR7 DMAC_DSAR(7) +#define DMAC_DDAR7 DMAC_DDAR(7) +#define DMAC_DTCR7 DMAC_DTCR(7) +#define DMAC_DRSR7 DMAC_DRSR(7) +#define DMAC_DCCSR7 DMAC_DCCSR(7) + + + +/************************************************************************* + * AIC + *************************************************************************/ +#define AIC_FR REG32 (AIC_BASE + 0x000) +#define AIC_CR REG32 (AIC_BASE + 0x004) +#define AIC_ACCR1 REG32 (AIC_BASE + 0x008) +#define AIC_ACCR2 REG32 (AIC_BASE + 0x00C) +#define AIC_I2SCR REG32 (AIC_BASE + 0x010) +#define AIC_SR REG32 (AIC_BASE + 0x014) +#define AIC_ACSR REG32 (AIC_BASE + 0x018) +#define AIC_I2SSR REG32 (AIC_BASE + 0x01C) +#define AIC_ACCAR REG32 (AIC_BASE + 0x020) +#define AIC_ACCDR REG32 (AIC_BASE + 0x024) +#define AIC_ACSAR REG32 (AIC_BASE + 0x028) +#define AIC_ACSDR REG32 (AIC_BASE + 0x02C) +#define AIC_I2SDIV REG32 (AIC_BASE + 0x030) +#define AIC_DR REG32 (AIC_BASE + 0x034) + +/* AIC Controller Configuration Register (AIC_FR) */ + +#define AIC_FR_RFTH_BIT 12 +#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) +#define AIC_FR_TFTH_BIT 8 +#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) +#define AIC_FR_AUSEL (1 << 4) +#define AIC_FR_RST (1 << 3) +#define AIC_FR_BCKD (1 << 2) +#define AIC_FR_SYNCD (1 << 1) +#define AIC_FR_ENB (1 << 0) + +/* AIC Controller Common Control Register (AIC_CR) */ + +#define AIC_CR_RDMS (1 << 15) +#define AIC_CR_TDMS (1 << 14) +#define AIC_CR_FLUSH (1 << 8) +#define AIC_CR_EROR (1 << 6) +#define AIC_CR_ETUR (1 << 5) +#define AIC_CR_ERFS (1 << 4) +#define AIC_CR_ETFS (1 << 3) +#define AIC_CR_ENLBF (1 << 2) +#define AIC_CR_ERPL (1 << 1) +#define AIC_CR_EREC (1 << 0) + +/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ + +#define AIC_ACCR1_RS_BIT 16 +#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) + #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ + #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ + #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ + #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ + #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ + #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ + #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ + #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ + #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ + #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ +#define AIC_ACCR1_XS_BIT 0 +#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) + #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ + #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ + #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ + #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ + #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ + #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ + #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ + #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ + #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ + #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ + +/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ + +#define AIC_ACCR2_ERSTO (1 << 18) +#define AIC_ACCR2_ESADR (1 << 17) +#define AIC_ACCR2_ECADT (1 << 16) +#define AIC_ACCR2_OASS_BIT 8 +#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) + #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ + #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ + #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ + #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ +#define AIC_ACCR2_IASS_BIT 6 +#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) + #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ + #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ + #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ + #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ +#define AIC_ACCR2_SO (1 << 3) +#define AIC_ACCR2_SR (1 << 2) +#define AIC_ACCR2_SS (1 << 1) +#define AIC_ACCR2_SA (1 << 0) + +/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ + +#define AIC_I2SCR_STPBK (1 << 12) +#define AIC_I2SCR_WL_BIT 1 +#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) + #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ + #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ + #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ + #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ + #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ +#define AIC_I2SCR_AMSL (1 << 0) + +/* AIC Controller FIFO Status Register (AIC_SR) */ + +#define AIC_SR_RFL_BIT 24 +#define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) +#define AIC_SR_TFL_BIT 8 +#define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) +#define AIC_SR_ROR (1 << 6) +#define AIC_SR_TUR (1 << 5) +#define AIC_SR_RFS (1 << 4) +#define AIC_SR_TFS (1 << 3) + +/* AIC Controller AC-link Status Register (AIC_ACSR) */ + +#define AIC_ACSR_CRDY (1 << 20) +#define AIC_ACSR_CLPM (1 << 19) +#define AIC_ACSR_RSTO (1 << 18) +#define AIC_ACSR_SADR (1 << 17) +#define AIC_ACSR_CADT (1 << 16) + +/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ + +#define AIC_I2SSR_BSY (1 << 2) + +/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ + +#define AIC_ACCAR_CAR_BIT 0 +#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) + +/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ + +#define AIC_ACCDR_CDR_BIT 0 +#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) + +/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ + +#define AIC_ACSAR_SAR_BIT 0 +#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) + +/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ + +#define AIC_ACSDR_SDR_BIT 0 +#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) + +/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ + +#define AIC_I2SDIV_DIV_BIT 0 +#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) + #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ + #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ + #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ + #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ + #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ + #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ + + + + +/************************************************************************* + * LCD + *************************************************************************/ +#define LCD_CFG REG32 (LCD_BASE + 0x00) +#define LCD_VSYNC REG32 (LCD_BASE + 0x04) +#define LCD_HSYNC REG32 (LCD_BASE + 0x08) +#define LCD_VAT REG32 (LCD_BASE + 0x0c) +#define LCD_DAH REG32 (LCD_BASE + 0x10) +#define LCD_DAV REG32 (LCD_BASE + 0x14) +#define LCD_PS REG32 (LCD_BASE + 0x18) +#define LCD_CLS REG32 (LCD_BASE + 0x1c) +#define LCD_SPL REG32 (LCD_BASE + 0x20) +#define LCD_REV REG32 (LCD_BASE + 0x24) +#define LCD_CTRL REG32 (LCD_BASE + 0x30) +#define LCD_STATE REG32 (LCD_BASE + 0x34) +#define LCD_IID REG32 (LCD_BASE + 0x38) +#define LCD_DA0 REG32 (LCD_BASE + 0x40) +#define LCD_SA0 REG32 (LCD_BASE + 0x44) +#define LCD_FID0 REG32 (LCD_BASE + 0x48) +#define LCD_CMD0 REG32 (LCD_BASE + 0x4c) +#define LCD_DA1 REG32 (LCD_BASE + 0x50) +#define LCD_SA1 REG32 (LCD_BASE + 0x54) +#define LCD_FID1 REG32 (LCD_BASE + 0x58) +#define LCD_CMD1 REG32 (LCD_BASE + 0x5c) + +#define LCD_CFG_PDW_BIT 4 +#define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) +#define LCD_CFG_MODE_BIT 0 +#define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) + +#define LCD_VSYNC_VPS_BIT 16 +#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) +#define LCD_VSYNC_VPE_BIT 0 +#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) + +#define LCD_HSYNC_HPS_BIT 16 +#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) +#define LCD_HSYNC_HPE_BIT 0 +#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) + +#define LCD_VAT_HT_BIT 16 +#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) +#define LCD_VAT_VT_BIT 0 +#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) + +#define LCD_DAH_HDS_BIT 16 +#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) +#define LCD_DAH_HDE_BIT 0 +#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) + +#define LCD_DAV_VDS_BIT 16 +#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) +#define LCD_DAV_VDE_BIT 0 +#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) + +#define LCD_CTRL_BST_BIT 28 +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) +#define LCD_CTRL_RGB555 (1 << 27) +#define LCD_CTRL_OFUP (1 << 26) +#define LCD_CTRL_FRC_BIT 24 +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) +#define LCD_CTRL_PDD_BIT 16 +#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) +#define LCD_CTRL_EOFM (1 << 13) +#define LCD_CTRL_SOFM (1 << 12) +#define LCD_CTRL_OFUM (1 << 11) +#define LCD_CTRL_IFUM0 (1 << 10) +#define LCD_CTRL_IFUM1 (1 << 9) +#define LCD_CTRL_LDDM (1 << 8) +#define LCD_CTRL_QDM (1 << 7) +#define LCD_CTRL_BEDN (1 << 6) +#define LCD_CTRL_PEDN (1 << 5) +#define LCD_CTRL_DIS (1 << 4) +#define LCD_CTRL_ENA (1 << 3) +#define LCD_CTRL_BPP_BIT 0 +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) + +#define LCD_STATE_QD (1 << 7) +#define LCD_STATE_EOF (1 << 5) +#define LCD_STATE_SOF (1 << 4) +#define LCD_STATE_OFU (1 << 3) +#define LCD_STATE_IFU0 (1 << 2) +#define LCD_STATE_IFU1 (1 << 1) +#define LCD_STATE_LDD (1 << 0) + +#define LCD_CMD_SOFINT (1 << 31) +#define LCD_CMD_EOFINT (1 << 30) +#define LCD_CMD_PAL (1 << 28) +#define LCD_CMD_LEN_BIT 0 +#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) + + + + +/************************************************************************* + * DES + *************************************************************************/ +#define DES_CR1 REG32 (DES_BASE + 0x000) +#define DES_CR2 REG32 (DES_BASE + 0x004) +#define DES_SR REG32 (DES_BASE + 0x008) +#define DES_K1L REG32 (DES_BASE + 0x010) +#define DES_K1R REG32 (DES_BASE + 0x014) +#define DES_K2L REG32 (DES_BASE + 0x018) +#define DES_K2R REG32 (DES_BASE + 0x01C) +#define DES_K3L REG32 (DES_BASE + 0x020) +#define DES_K3R REG32 (DES_BASE + 0x024) +#define DES_IVL REG32 (DES_BASE + 0x028) +#define DES_IVR REG32 (DES_BASE + 0x02C) +#define DES_DIN REG32 (DES_BASE + 0x030) +#define DES_DOUT REG32 (DES_BASE + 0x034) + +/* DES Control Register 1 (DES_CR1) */ + +#define DES_CR1_EN (1 << 0) + +/* DES Control Register 2 (DES_CR2) */ + +#define DES_CR2_ENDEC (1 << 3) +#define DES_CR2_MODE (1 << 2) +#define DES_CR2_ALG (1 << 1) +#define DES_CR2_DMAE (1 << 0) + +/* DES State Register (DES_SR) */ + +#define DES_SR_IN_FULL (1 << 5) +#define DES_SR_IN_LHF (1 << 4) +#define DES_SR_IN_EMPTY (1 << 3) +#define DES_SR_OUT_FULL (1 << 2) +#define DES_SR_OUT_GHF (1 << 1) +#define DES_SR_OUT_EMPTY (1 << 0) + + + + +/************************************************************************* + * CPM + *************************************************************************/ +#define CPM_CFCR REG32 (CPM_BASE+0x00) +#define CPM_PLCR1 REG32 (CPM_BASE+0x10) +#define CPM_OCR REG32 (CPM_BASE+0x1c) +#define CPM_CFCR2 REG32 (CPM_BASE+0x60) +#define CPM_LPCR REG32 (CPM_BASE+0x04) +#define CPM_RSTR REG32 (CPM_BASE+0x08) +#define CPM_MSCR REG32 (CPM_BASE+0x20) +#define CPM_SCR REG32 (CPM_BASE+0x24) +#define CPM_WRER REG32 (CPM_BASE+0x28) +#define CPM_WFER REG32 (CPM_BASE+0x2c) +#define CPM_WER REG32 (CPM_BASE+0x30) +#define CPM_WSR REG32 (CPM_BASE+0x34) +#define CPM_GSR0 REG32 (CPM_BASE+0x38) +#define CPM_GSR1 REG32 (CPM_BASE+0x3c) +#define CPM_GSR2 REG32 (CPM_BASE+0x40) +#define CPM_SPR REG32 (CPM_BASE+0x44) +#define CPM_GSR3 REG32 (CPM_BASE+0x48) + +#define CPM_CFCR_SSI (1 << 31) +#define CPM_CFCR_LCD (1 << 30) +#define CPM_CFCR_I2S (1 << 29) +#define CPM_CFCR_UCS (1 << 28) +#define CPM_CFCR_UFR_BIT 25 +#define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) +#define CPM_CFCR_MSC (1 << 24) +#define CPM_CFCR_CKOEN2 (1 << 23) +#define CPM_CFCR_CKOEN1 (1 << 22) +#define CPM_CFCR_UPE (1 << 20) +#define CPM_CFCR_MFR_BIT 16 +#define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) +#define CPM_CFCR_LFR_BIT 12 +#define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) +#define CPM_CFCR_PFR_BIT 8 +#define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) +#define CPM_CFCR_SFR_BIT 4 +#define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) +#define CPM_CFCR_IFR_BIT 0 +#define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) + +#define CPM_PLCR1_PLL1FD_BIT 23 +#define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) +#define CPM_PLCR1_PLL1RD_BIT 18 +#define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) +#define CPM_PLCR1_PLL1OD_BIT 16 +#define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) +#define CPM_PLCR1_PLL1S (1 << 10) +#define CPM_PLCR1_PLL1BP (1 << 9) +#define CPM_PLCR1_PLL1EN (1 << 8) +#define CPM_PLCR1_PLL1ST_BIT 0 +#define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) + +#define CPM_OCR_O1ST_BIT 16 +#define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) +#define CPM_OCR_EXT_RTC_CLK (1<<8) +#define CPM_OCR_SUSPEND_PHY1 (1<<7) +#define CPM_OCR_SUSPEND_PHY0 (1<<6) + +#define CPM_CFCR2_PXFR_BIT 0 +#define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) + +#define CPM_LPCR_DUTY_BIT 3 +#define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) +#define CPM_LPCR_DOZE (1 << 2) +#define CPM_LPCR_LPM_BIT 0 +#define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) + #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) + #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) + #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) + +#define CPM_RSTR_SR (1 << 2) +#define CPM_RSTR_WR (1 << 1) +#define CPM_RSTR_HR (1 << 0) + +#define CPM_MSCR_MSTP_BIT 0 +#define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) + #define CPM_MSCR_MSTP_UART0 0 + #define CPM_MSCR_MSTP_UART1 1 + #define CPM_MSCR_MSTP_UART2 2 + #define CPM_MSCR_MSTP_OST 3 + #define CPM_MSCR_MSTP_DMAC 5 + #define CPM_MSCR_MSTP_UHC 6 + #define CPM_MSCR_MSTP_LCD 7 + #define CPM_MSCR_MSTP_I2C 8 + #define CPM_MSCR_MSTP_AICPCLK 9 + #define CPM_MSCR_MSTP_PWM0 10 + #define CPM_MSCR_MSTP_PWM1 11 + #define CPM_MSCR_MSTP_SSI 12 + #define CPM_MSCR_MSTP_MSC 13 + #define CPM_MSCR_MSTP_SCC 14 + #define CPM_MSCR_MSTP_AICBCLK 18 + #define CPM_MSCR_MSTP_UART3 20 + #define CPM_MSCR_MSTP_ETH 21 + #define CPM_MSCR_MSTP_KBC 22 + #define CPM_MSCR_MSTP_CIM 23 + #define CPM_MSCR_MSTP_UDC 24 + #define CPM_MSCR_MSTP_UPRT 25 + +#define CPM_SCR_O1SE (1 << 4) +#define CPM_SCR_HGP (1 << 3) +#define CPM_SCR_HZP (1 << 2) +#define CPM_SCR_HZM (1 << 1) + +#define CPM_WRER_RE_BIT 0 +#define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) + +#define CPM_WFER_FE_BIT 0 +#define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) + +#define CPM_WER_WERTC (1 << 31) +#define CPM_WER_WEETH (1 << 30) +#define CPM_WER_WE_BIT 0 +#define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) + +#define CPM_WSR_WSRTC (1 << 31) +#define CPM_WSR_WSETH (1 << 30) +#define CPM_WSR_WS_BIT 0 +#define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) + + + + +/************************************************************************* + * SSI + *************************************************************************/ +#define SSI_DR REG32 (SSI_BASE + 0x001) +#define SSI_CR0 REG16 (SSI_BASE + 0x004) +#define SSI_CR1 REG32 (SSI_BASE + 0x008) +#define SSI_SR REG32 (SSI_BASE + 0x00C) +#define SSI_ITR REG16 (SSI_BASE + 0x010) +#define SSI_ICR REG8 (SSI_BASE + 0x014) +#define SSI_GR REG16 (SSI_BASE + 0x018) + +/* SSI Data Register (SSI_DR) */ + +#define SSI_DR_GPC_BIT 0 +#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) + +/* SSI Control Register 0 (SSI_CR0) */ + +#define SSI_CR0_SSIE (1 << 15) +#define SSI_CR0_TIE (1 << 14) +#define SSI_CR0_RIE (1 << 13) +#define SSI_CR0_TEIE (1 << 12) +#define SSI_CR0_REIE (1 << 11) +#define SSI_CR0_LOOP (1 << 10) +#define SSI_CR0_RFINE (1 << 9) +#define SSI_CR0_RFINC (1 << 8) +#define SSI_CR0_FSEL (1 << 6) +#define SSI_CR0_TFLUSH (1 << 2) +#define SSI_CR0_RFLUSH (1 << 1) +#define SSI_CR0_DISREV (1 << 0) + +/* SSI Control Register 1 (SSI_CR1) */ + +#define SSI_CR1_FRMHL_BIT 30 +#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) + #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ + #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ + #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ + #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ +#define SSI_CR1_TFVCK_BIT 28 +#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) + #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) +#define SSI_CR1_TCKFI_BIT 26 +#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) + #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) +#define SSI_CR1_LFST (1 << 25) +#define SSI_CR1_ITFRM (1 << 24) +#define SSI_CR1_UNFIN (1 << 23) +#define SSI_CR1_MULTS (1 << 22) +#define SSI_CR1_FMAT_BIT 20 +#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) + #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ + #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ + #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ + #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ +#define SSI_CR1_MCOM_BIT 12 +#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) + #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ + #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ + #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ + #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ + #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ + #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ + #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ + #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ + #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ + #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ + #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ + #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ + #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ + #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ + #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ + #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ +#define SSI_CR1_TTRG_BIT 10 +#define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) + #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ + #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ + #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ + #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ +#define SSI_CR1_RTRG_BIT 8 +#define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) + #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ + #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ + #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ + #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ +#define SSI_CR1_FLEN_BIT 4 +#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) + #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) +#define SSI_CR1_PHA (1 << 1) +#define SSI_CR1_POL (1 << 0) + +/* SSI Status Register (SSI_SR) */ + +#define SSI_SR_TFIFONUM_BIT 13 +#define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) +#define SSI_SR_RFIFONUM_BIT 8 +#define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) +#define SSI_SR_END (1 << 7) +#define SSI_SR_BUSY (1 << 6) +#define SSI_SR_TFF (1 << 5) +#define SSI_SR_RFE (1 << 4) +#define SSI_SR_TFHE (1 << 3) +#define SSI_SR_RFHF (1 << 2) +#define SSI_SR_UNDR (1 << 1) +#define SSI_SR_OVER (1 << 0) + +/* SSI Interval Time Control Register (SSI_ITR) */ + +#define SSI_ITR_CNTCLK (1 << 15) +#define SSI_ITR_IVLTM_BIT 0 +#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) + + +//################### operations ###################################### + +/*************************************************************************** + * MSC + ***************************************************************************/ + +#define msc_start_op() ( MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) + +#define msc_set_resto(to) ( MSC_RESTO = to ) +#define msc_set_rdto(to) ( MSC_RDTO = to ) +#define msc_set_cmd(cmd) ( MSC_CMD = cmd ) +#define msc_set_arg(arg) ( MSC_ARG = arg ) +#define msc_set_nob(nob) ( MSC_NOB = nob ) +#define msc_get_nob() ( MSC_NOB ) +#define msc_set_blklen(len) ( MSC_BLKLEN = len ) +#define msc_set_cmdat(cmdat) ( MSC_CMDAT = cmdat ) +#define msc_set_cmdat_ioabort() ( MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) +#define msc_clear_cmdat_ioabort() ( MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) + +#define msc_set_cmdat_bus_width1() do { MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; } while(0) + +#define msc_set_cmdat_bus_width4() do { MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; } while(0) + +#define msc_set_cmdat_dma_en() ( MSC_CMDAT |= MSC_CMDAT_DMA_EN ) +#define msc_set_cmdat_init() ( MSC_CMDAT |= MSC_CMDAT_INIT ) +#define msc_set_cmdat_busy() ( MSC_CMDAT |= MSC_CMDAT_BUSY ) +#define msc_set_cmdat_stream() ( MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) +#define msc_set_cmdat_block() ( MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) +#define msc_set_cmdat_read() ( MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) +#define msc_set_cmdat_write() ( MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) +#define msc_set_cmdat_data_en() ( MSC_CMDAT |= MSC_CMDAT_DATA_EN ) + +/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ +#define msc_set_cmdat_res_format(r) do { MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; MSC_CMDAT |= (r); } while(0) + +#define msc_clear_cmdat() do { MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ); } while (0) + +#define msc_get_imask() ( MSC_IMASK ) +#define msc_mask_all_intrs() ( MSC_IMASK = 0xff ) +#define msc_unmask_all_intrs() ( MSC_IMASK = 0x00 ) +#define msc_mask_rd() ( MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) +#define msc_unmask_rd() ( MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) +#define msc_mask_wr() ( MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) +#define msc_unmask_wr() ( MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) +#define msc_mask_endcmdres() ( MSC_IMASK |= MSC_IMASK_END_CMD_RES ) +#define msc_unmask_endcmdres() ( MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) +#define msc_mask_datatrandone() ( MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) +#define msc_unmask_datatrandone() ( MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) +#define msc_mask_prgdone() ( MSC_IMASK |= MSC_IMASK_PRG_DONE ) +#define msc_unmask_prgdone() ( MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) + +/* n=0,1,2,3,4,5,6,7 */ +#define msc_set_clkrt(n) do { MSC_CLKRT = n; } while(0) + +#define msc_get_ireg() ( MSC_IREG ) +#define msc_ireg_rd() ( MSC_IREG & MSC_IRXFIFO_RD_REQ ) +#define msc_ireg_wr() ( MSC_IREG & MSC_ITXFIFO_WR_REQ ) +#define msc_ireg_end_cmd_res() ( MSC_IREG & MSC_IEND_CMD_RES ) +#define msc_ireg_data_tran_done() ( MSC_IREG & MSC_IDATA_TRAN_DONE ) +#define msc_ireg_prg_done() ( MSC_IREG & MSC_IPRG_DONE ) +#define msc_ireg_clear_end_cmd_res() ( MSC_IREG = MSC_IEND_CMD_RES ) +#define msc_ireg_clear_data_tran_done() ( MSC_IREG = MSC_IDATA_TRAN_DONE ) +#define msc_ireg_clear_prg_done() ( MSC_IREG = MSC_IPRG_DONE ) + +#define msc_get_stat() ( MSC_STAT ) +#define msc_stat_not_end_cmd_res() ( (MSC_STAT & MSC_STAT_END_CMD_RES) == 0) +#define msc_stat_crc_err() ( MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) +#define msc_stat_res_crc_err() ( MSC_STAT & MSC_STAT_CRC_RES_ERR ) +#define msc_stat_rd_crc_err() ( MSC_STAT & MSC_STAT_CRC_READ_ERROR ) +#define msc_stat_wr_crc_err() ( MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) +#define msc_stat_resto_err() ( MSC_STAT & MSC_STAT_TIME_OUT_RES ) +#define msc_stat_rdto_err() ( MSC_STAT & MSC_STAT_TIME_OUT_READ ) + +#define msc_rd_resfifo() ( MSC_RES ) +#define msc_rd_rxfifo() ( MSC_RXFIFO ) +#define msc_wr_txfifo(v) ( MSC_TXFIFO = v ) + +#define msc_reset() do { MSC_STRPCL = MSC_STRPCL_RESET; while (MSC_STAT & MSC_STAT_IS_RESETTING); } while (0) + +#define msc_start_clk() do { MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; } while (0) + +#define msc_stop_clk() do { MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; } while (0) + +#define MMC_CLK 19169200 +#define SD_CLK 24576000 + +/* msc_clk should little than pclk and little than clk retrieve from card */ +static __inline__ unsigned msc_calc_clk_divisor (bool is_sd, unsigned dev_clk, unsigned msc_clk): + unsigned rate, ret + rate = is_sd ? SD_CLK : MMC_CLK + if (msc_clk && msc_clk < dev_clk) + dev_clk = msc_clk + for ret = 0; dev_clk < rate; ++ret, rate >>= 1: + return ret + return 0 + +/* divide rate to little than or equal to 400kHz */ +static __inline__ unsigned msc_calc_slow_clk_divisor (bool is_s): + unsigned rate, ret + rate = (is_sd ? SD_CLK : MMC_CLK) / 1000 / 400 + for ret = 0; rate > 0; rate >>= 1, ++ret: + return ret + +/*************************************************************************** + * RTC + ***************************************************************************/ + +#define rtc_start() ( RTC_RCR |= RTC_RCR_START ) +#define rtc_stop() ( RTC_RCR &= ~RTC_RCR_START ) + +#define rtc_enable_alarm() ( RTC_RCR |= RTC_RCR_AE ) +#define rtc_disable_alarm() ( RTC_RCR &= ~RTC_RCR_AE ) +#define rtc_enable_alarm_irq() ( RTC_RCR |= RTC_RCR_AIE ) +#define rtc_disable_alarm_irq() ( RTC_RCR &= ~RTC_RCR_AIE ) + +#define rtc_enable_1hz_irq() ( RTC_RCR |= RTC_RCR_HZIE ) +#define rtc_disable_1hz_irq() ( RTC_RCR &= ~RTC_RCR_HZIE ) + +#define rtc_is_alarm_flag() ( RTC_RCR & RTC_RCR_AF ) +#define rtc_is_1hz_flag() ( RTC_RCR & RTC_RCR_HZ ) +#define rtc_clear_alarm_flag() ( RTC_RCR &= ~RTC_RCR_AF ) +#define rtc_clear_1hz_flag() ( RTC_RCR &= ~RTC_RCR_HZ ) + +#define rtc_set_second(s) ( RTC_RSR = (s) ) +#define rtc_get_second() RTC_RSR +#define rtc_set_alarm(s) ( RTC_RSAR = (s) ) +#define rtc_get_alarm() RTC_RSAR + +#define rtc_adjust_1hz(f32k) ( RTC_RGR = (RTC_RGR & ~(RTC_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) +#define rtc_lock_1hz() ( RTC_RGR |= RTC_RGR_LOCK ) + + +/*************************************************************************** + * FIR + ***************************************************************************/ + +/* enable/disable fir unit */ +#define fir_enable() ( FIR_CR1 |= FIR_CR1_FIRUE ) +#define fir_disable() ( FIR_CR1 &= ~FIR_CR1_FIRUE ) + +/* enable/disable address comparison */ +#define fir_enable_ac() ( FIR_CR1 |= FIR_CR1_ACE ) +#define fir_disable_ac() ( FIR_CR1 &= ~FIR_CR1_ACE ) + +/* select frame end mode as underrun or normal */ +#define fir_set_eous() ( FIR_CR1 |= FIR_CR1_EOUS ) +#define fir_clear_eous() ( FIR_CR1 &= ~FIR_CR1_EOUS ) + +/* enable/disable transmitter idle interrupt */ +#define fir_enable_tii() ( FIR_CR1 |= FIR_CR1_TIIE ) +#define fir_disable_tii() ( FIR_CR1 &= ~FIR_CR1_TIIE ) + +/* enable/disable transmit FIFO service request interrupt */ +#define fir_enable_tfi() ( FIR_CR1 |= FIR_CR1_TFIE ) +#define fir_disable_tfi() ( FIR_CR1 &= ~FIR_CR1_TFIE ) + +/* enable/disable receive FIFO service request interrupt */ +#define fir_enable_rfi() ( FIR_CR1 |= FIR_CR1_RFIE ) +#define fir_disable_rfi() ( FIR_CR1 &= ~FIR_CR1_RFIE ) + +/* enable/disable tx function */ +#define fir_tx_enable() ( FIR_CR1 |= FIR_CR1_TXE ) +#define fir_tx_disable() ( FIR_CR1 &= ~FIR_CR1_TXE ) + +/* enable/disable rx function */ +#define fir_rx_enable() ( FIR_CR1 |= FIR_CR1_RXE ) +#define fir_rx_disable() ( FIR_CR1 &= ~FIR_CR1_RXE ) + + +/* enable/disable serial infrared interaction pulse (SIP) */ +#define fir_enable_sip() ( FIR_CR2 |= FIR_CR2_SIPE ) +#define fir_disable_sip() ( FIR_CR2 &= ~FIR_CR2_SIPE ) + +/* un-inverted CRC value is sent out */ +#define fir_enable_bcrc() ( FIR_CR2 |= FIR_CR2_BCRC ) + +/* inverted CRC value is sent out */ +#define fir_disable_bcrc() ( FIR_CR2 &= ~FIR_CR2_BCRC ) + +/* enable/disable Transmit Frame Length Register */ +#define fir_enable_tflr() ( FIR_CR2 |= FIR_CR2_TFLRS ) +#define fir_disable_tflr() ( FIR_CR2 &= ~FIR_CR2_TFLRS ) + +/* Preamble is transmitted in idle state */ +#define fir_set_iss() ( FIR_CR2 |= FIR_CR2_ISS ) + +/* Abort symbol is transmitted in idle state */ +#define fir_clear_iss() ( FIR_CR2 &= ~FIR_CR2_ISS ) + +/* enable/disable loopback mode */ +#define fir_enable_loopback() ( FIR_CR2 |= FIR_CR2_LMS ) +#define fir_disable_loopback() ( FIR_CR2 &= ~FIR_CR2_LMS ) + +/* select transmit pin polarity */ +#define fir_tpp_negative() ( FIR_CR2 |= FIR_CR2_TPPS ) +#define fir_tpp_positive() ( FIR_CR2 &= ~FIR_CR2_TPPS ) + +/* select receive pin polarity */ +#define fir_rpp_negative() ( FIR_CR2 |= FIR_CR2_RPPS ) +#define fir_rpp_positive() ( FIR_CR2 &= ~FIR_CR2_RPPS ) + +/* n=16,32,64,128 */ +#define fir_set_txfifo_trigger(n) do { FIR_CR2 &= ~FIR_CR2_TTRG_MASK; FIR_CR2 |= FIR_CR2_TTRG_##n; } while (0) + +/* n=16,32,64,128 */ +#define fir_set_rxfifo_trigger(n) do { FIR_CR2 &= ~FIR_CR2_RTRG_MASK; FIR_CR2 |= FIR_CR2_RTRG_##n; } while (0) + + +/* FIR status checking */ + +#define fir_test_rfw() ( FIR_SR & FIR_SR_RFW ) +#define fir_test_rfa() ( FIR_SR & FIR_SR_RFA ) +#define fir_test_tfrtl() ( FIR_SR & FIR_SR_TFRTL ) +#define fir_test_rfrtl() ( FIR_SR & FIR_SR_RFRTL ) +#define fir_test_urun() ( FIR_SR & FIR_SR_URUN ) +#define fir_test_rfte() ( FIR_SR & FIR_SR_RFTE ) +#define fir_test_orun() ( FIR_SR & FIR_SR_ORUN ) +#define fir_test_crce() ( FIR_SR & FIR_SR_CRCE ) +#define fir_test_fend() ( FIR_SR & FIR_SR_FEND ) +#define fir_test_tff() ( FIR_SR & FIR_SR_TFF ) +#define fir_test_rfe() ( FIR_SR & FIR_SR_RFE ) +#define fir_test_tidle() ( FIR_SR & FIR_SR_TIDLE ) +#define fir_test_rb() ( FIR_SR & FIR_SR_RB ) + +#define fir_clear_status() do { FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; } while (0) + +#define fir_clear_rfw() ( FIR_SR |= FIR_SR_RFW ) +#define fir_clear_rfa() ( FIR_SR |= FIR_SR_RFA ) +#define fir_clear_urun() ( FIR_SR |= FIR_SR_URUN ) + +#define fir_set_tflr(len) do { FIR_TFLR = len; } while (0) + +#define fir_set_addr(a) ( FIR_AR = (a) ) + +#define fir_write_data(data) ( FIR_TDR = data ) +#define fir_read_data(data) ( data = FIR_RDR ) + +/*************************************************************************** + * SCC + ***************************************************************************/ + +#define scc_enable(base) ( SCC_CR(base) |= SCC_CR_SCCE ) +#define scc_disable(base) ( SCC_CR(base) &= ~SCC_CR_SCCE ) + +#define scc_set_tx_mode(base) ( SCC_CR(base) |= SCC_CR_TRS ) +#define scc_set_rx_mode(base) ( SCC_CR(base) &= ~SCC_CR_TRS ) + +#define scc_enable_t2r(base) ( SCC_CR(base) |= SCC_CR_T2R ) +#define scc_disable_t2r(base) ( SCC_CR(base) &= ~SCC_CR_T2R ) + +#define scc_clk_as_devclk(base) do { SCC_CR(base) &= ~SCC_CR_FDIV_MASK; SCC_CR(base) |= SCC_CR_FDIV_1; } while (0) + +#define scc_clk_as_half_devclk(base) do { SCC_CR(base) &= ~SCC_CR_FDIV_MASK; SCC_CR(base) |= SCC_CR_FDIV_2; } while (0) + +/* n=1,4,8,14 */ +#define scc_set_fifo_trigger(base, n) do { SCC_CR(base) &= ~SCC_CR_TRIG_MASK; SCC_CR(base) |= SCC_CR_TRIG_##n; } while (0) + +#define scc_set_protocol(base, p) do { if (p) SCC_CR(base) |= SCC_CR_TP; else SCC_CR(base) &= ~SCC_CR_TP; } while (0) + +#define scc_flush_fifo(base) ( SCC_CR(base) |= SCC_CR_FLUSH ) + +#define scc_set_invert_mode(base) ( SCC_CR(base) |= SCC_CR_CONV ) +#define scc_set_direct_mode(base) ( SCC_CR(base) &= ~SCC_CR_CONV ) + +#define SCC_ERR_INTRS ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) +#define SCC_ALL_INTRS ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) + +#define scc_enable_err_intrs(base) ( SCC_CR(base) |= SCC_ERR_INTRS ) +#define scc_disable_err_intrs(base) ( SCC_CR(base) &= ~SCC_ERR_INTRS ) + +#define SCC_ALL_ERRORS ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) + +#define scc_clear_errors(base) ( SCC_SR(base) &= ~SCC_ALL_ERRORS ) + +#define scc_enable_all_intrs(base) ( SCC_CR(base) |= SCC_ALL_INTRS ) +#define scc_disable_all_intrs(base) ( SCC_CR(base) &= ~SCC_ALL_INTRS ) + +#define scc_enable_tx_intr(base) ( SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) +#define scc_disable_tx_intr(base) ( SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) + +#define scc_enable_rx_intr(base) ( SCC_CR(base) |= SCC_CR_RXIE) +#define scc_disable_rx_intr(base) ( SCC_CR(base) &= ~SCC_CR_RXIE) + +#define scc_set_tsend(base) ( SCC_CR(base) |= SCC_CR_TSEND ) +#define scc_clear_tsend(base) ( SCC_CR(base) &= ~SCC_CR_TSEND ) + +#define scc_set_clockstop(base) ( SCC_CR(base) |= SCC_CR_CLKSTP ) +#define scc_clear_clockstop(base) ( SCC_CR(base) &= ~SCC_CR_CLKSTP ) + +#define scc_clockstop_low(base) do { SCC_CR(base) &= ~SCC_CR_PX_MASK; SCC_CR(base) |= SCC_CR_PX_STOP_LOW; } while (0) + +#define scc_clockstop_high(base) do { SCC_CR(base) &= ~SCC_CR_PX_MASK; SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; } while (0) + + +/* SCC status checking */ +#define scc_check_transfer_status(base) ( SCC_SR(base) & SCC_SR_TRANS ) +#define scc_check_rx_overrun_error(base) ( SCC_SR(base) & SCC_SR_ORER ) +#define scc_check_rx_timeout(base) ( SCC_SR(base) & SCC_SR_RTO ) +#define scc_check_parity_error(base) ( SCC_SR(base) & SCC_SR_PER ) +#define scc_check_txfifo_trigger(base) ( SCC_SR(base) & SCC_SR_TFTG ) +#define scc_check_rxfifo_trigger(base) ( SCC_SR(base) & SCC_SR_RFTG ) +#define scc_check_tx_end(base) ( SCC_SR(base) & SCC_SR_TEND ) +#define scc_check_retx_3(base) ( SCC_SR(base) & SCC_SR_RETR_3 ) +#define scc_check_ecnt_overflow(base) ( SCC_SR(base) & SCC_SR_ECNTO ) + + +/*************************************************************************** + * WDT + ***************************************************************************/ + +#define wdt_set_count(count) ( WDT_WTCNT = (count) ) +#define wdt_start() ( WDT_WTCSR |= WDT_WTCSR_START ) +#define wdt_stop() ( WDT_WTCSR &= ~WDT_WTCSR_START ) + + +/*************************************************************************** + * OST + ***************************************************************************/ + +#define ost_enable_all() ( OST_TER |= 0x07 ) +#define ost_disable_all() ( OST_TER &= ~0x07 ) +#define ost_enable_channel(n) ( OST_TER |= (1 << (n)) ) +#define ost_disable_channel(n) ( OST_TER &= ~(1 << (n)) ) +#define ost_set_reload(n, val) ( OST_TRDR(n) = (val) ) +#define ost_set_count(n, val) ( OST_TCNT(n) = (val) ) +#define ost_get_count(n) ( OST_TCNT(n) ) +#define ost_set_clock(n, cs) do { OST_TCSR(n) &= ~OST_TCSR_CKS_MASK; OST_TCSR(n) |= cs; } while (0) +#define ost_set_mode(n, val) ( OST_TCSR(n) = (val) ) +#define ost_enable_interrupt(n) ( OST_TCSR(n) |= OST_TCSR_UIE ) +#define ost_disable_interrupt(n) ( OST_TCSR(n) &= ~OST_TCSR_UIE ) +#define ost_uf_detected(n) ( OST_TCSR(n) & OST_TCSR_UF ) +#define ost_clear_uf(n) ( OST_TCSR(n) &= ~OST_TCSR_UF ) +#define ost_is_busy(n) ( OST_TCSR(n) & OST_TCSR_BUSY ) +#define ost_clear_busy(n) ( OST_TCSR(n) &= ~OST_TCSR_BUSY ) + + +/*************************************************************************** + * UART + ***************************************************************************/ + +#define uart_enable(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE ) +#define uart_disable(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) + +#define uart_enable_transmit_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) +#define uart_disable_transmit_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) + +#define uart_enable_receive_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) +#define uart_disable_receive_irq(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) + +#define uart_enable_loopback(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) +#define uart_disable_loopback(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) + +#define uart_set_8n1(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) + +#define uart_set_baud(n, devclk, baud) do { REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; } while (0) + +#define uart_parity_error(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) + +#define uart_clear_errors(n) ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) + +#define uart_transmit_fifo_empty(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) + +#define uart_transmit_end(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) + +#define uart_transmit_char(n, ch) REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) + +#define uart_receive_fifo_full(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) + +#define uart_receive_ready(n) ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) + +#define uart_receive_char(n) REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) + +#define uart_disable_irda() ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) +#define uart_enable_irda() /* Tx high pulse as 0, Rx low pulse as 0 */ ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) + + +/*************************************************************************** + * INTC + ***************************************************************************/ +#define intc_unmask_irq(n) ( INTC_IMCR = (1 << (n)) ) +#define intc_mask_irq(n) ( INTC_IMSR = (1 << (n)) ) +#define intc_ack_irq(n) ( INTC_IPR = (1 << (n)) ) + +/*************************************************************************** + * CIM + ***************************************************************************/ + +#define cim_enable() ( CIM_CTRL |= CIM_CTRL_ENA ) +#define cim_disable() ( CIM_CTRL &= ~CIM_CTRL_ENA ) + +#define cim_input_data_inverse() ( CIM_CFG |= CIM_CFG_INV_DAT ) +#define cim_input_data_normal() ( CIM_CFG &= ~CIM_CFG_INV_DAT ) + +#define cim_vsync_active_low() ( CIM_CFG |= CIM_CFG_VSP ) +#define cim_vsync_active_high() ( CIM_CFG &= ~CIM_CFG_VSP ) + +#define cim_hsync_active_low() ( CIM_CFG |= CIM_CFG_HSP ) +#define cim_hsync_active_high() ( CIM_CFG &= ~CIM_CFG_HSP ) + +#define cim_sample_data_at_pclk_falling_edge() ( CIM_CFG |= CIM_CFG_PCP ) +#define cim_sample_data_at_pclk_rising_edge() ( CIM_CFG &= ~CIM_CFG_PCP ) + +#define cim_enable_dummy_zero() ( CIM_CFG |= CIM_CFG_DUMMY_ZERO ) +#define cim_disable_dummy_zero() ( CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) + +#define cim_select_external_vsync() ( CIM_CFG |= CIM_CFG_EXT_VSYNC ) +#define cim_select_internal_vsync() ( CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) + +/* n=0-7 */ +#define cim_set_data_packing_mode(n) do { CIM_CFG &= ~CIM_CFG_PACK_MASK; CIM_CFG |= (CIM_CFG_PACK_##n); } while (0) + +#define cim_enable_ccir656_progressive_mode() do { CIM_CFG &= ~CIM_CFG_DSM_MASK; CIM_CFG |= CIM_CFG_DSM_CPM; } while (0) + +#define cim_enable_ccir656_interlace_mode() do { CIM_CFG &= ~CIM_CFG_DSM_MASK; CIM_CFG |= CIM_CFG_DSM_CIM; } while (0) + +#define cim_enable_gated_clock_mode() do { CIM_CFG &= ~CIM_CFG_DSM_MASK; CIM_CFG |= CIM_CFG_DSM_GCM; } while (0) + +#define cim_enable_nongated_clock_mode() do { CIM_CFG &= ~CIM_CFG_DSM_MASK; CIM_CFG |= CIM_CFG_DSM_NGCM; } while (0) + +/* sclk:system bus clock + * mclk: CIM master clock + */ +#define cim_set_master_clk(sclk, mclk) do { CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); } while (0) + +#define cim_enable_sof_intr() ( CIM_CTRL |= CIM_CTRL_DMA_SOFM ) +#define cim_disable_sof_intr() ( CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) + +#define cim_enable_eof_intr() ( CIM_CTRL |= CIM_CTRL_DMA_EOFM ) +#define cim_disable_eof_intr() ( CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) + +#define cim_enable_stop_intr() ( CIM_CTRL |= CIM_CTRL_DMA_STOPM ) +#define cim_disable_stop_intr() ( CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) + +#define cim_enable_trig_intr() ( CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) +#define cim_disable_trig_intr() ( CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) + +#define cim_enable_rxfifo_overflow_intr() ( CIM_CTRL |= CIM_CTRL_RXF_OFM ) +#define cim_disable_rxfifo_overflow_intr() ( CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) + +/* n=1-16 */ +#define cim_set_frame_rate(n) do { CIM_CTRL &= ~CIM_CTRL_FRC_MASK; CIM_CTRL |= CIM_CTRL_FRC_##n; } while (0) + +#define cim_enable_dma() ( CIM_CTRL |= CIM_CTRL_DMA_EN ) +#define cim_disable_dma() ( CIM_CTRL &= ~CIM_CTRL_DMA_EN ) + +#define cim_reset_rxfifo() ( CIM_CTRL |= CIM_CTRL_RXF_RST ) +#define cim_unreset_rxfifo() ( CIM_CTRL &= ~CIM_CTRL_RXF_RST ) + +/* n=4,8,12,16,20,24,28,32 */ +#define cim_set_rxfifo_trigger(n) do { CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; } while (0) + +#define cim_clear_state() ( CIM_STATE = 0 ) + +#define cim_disable_done() ( CIM_STATE & CIM_STATE_VDD ) +#define cim_rxfifo_empty() ( CIM_STATE & CIM_STATE_RXF_EMPTY ) +#define cim_rxfifo_reach_trigger() ( CIM_STATE & CIM_STATE_RXF_TRIG ) +#define cim_rxfifo_overflow() ( CIM_STATE & CIM_STATE_RXF_OF ) +#define cim_clear_rxfifo_overflow() ( CIM_STATE &= ~CIM_STATE_RXF_OF ) +#define cim_dma_stop() ( CIM_STATE & CIM_STATE_DMA_STOP ) +#define cim_dma_eof() ( CIM_STATE & CIM_STATE_DMA_EOF ) +#define cim_dma_sof() ( CIM_STATE & CIM_STATE_DMA_SOF ) + +#define cim_get_iid() ( CIM_IID ) +#define cim_get_image_data() ( CIM_RXFIFO ) +#define cim_get_dam_cmd() ( CIM_CMD ) + +#define cim_set_da(a) ( CIM_DA = (a) ) + +/*************************************************************************** + * PWM + ***************************************************************************/ + +/* n is the pwm channel (0,1,..) */ +#define pwm_enable_module(n) ( PWM_CTR(n) |= PWM_CTR_EN ) +#define pwm_disable_module(n) ( PWM_CTR(n) &= ~PWM_CTR_EN ) +#define pwm_graceful_shutdown_mode(n) ( PWM_CTR(n) &= ~PWM_CTR_SD ) +#define pwm_abrupt_shutdown_mode(n) ( PWM_CTR(n) |= PWM_CTR_SD ) +#define pwm_set_full_duty(n) ( PWM_DUT(n) |= PWM_DUT_FDUTY ) + +#define pwm_set_prescale(n, p) ( PWM_CTR(n) = ((PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) +#define pwm_set_period(n, p) ( PWM_PER(n) = ( (PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) +#define pwm_set_duty(n, d) ( PWM_DUT(n) = ( (PWM_DUT(n) & ~(PWM_DUT_FDUTY | PWM_DUT_DUTY_MASK)) | (d) ) ) + +/*************************************************************************** + * EMC + ***************************************************************************/ + +#define emc_enable_split() ( EMC_BCR = EMC_BCR_BRE ) +#define emc_disable_split() ( EMC_BCR = 0 ) + +#define emc_smem_bus_width(n) /* 8, 16 or 32*/ ( EMC_SMCR = (EMC_SMCR & EMC_SMCR_BW_MASK) | EMC_SMCR_BW_##n##BIT ) +#define emc_smem_byte_control() ( EMC_SMCR = (EMC_SMCR | EMC_SMCR_BCM ) ) +#define emc_normal_smem() ( EMC_SMCR = (EMC_SMCR & ~EMC_SMCR_SMT ) ) +#define emc_burst_smem() ( EMC_SMCR = (EMC_SMCR | EMC_SMCR_SMT ) ) +#define emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ ( EMC_SMCR = (EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n) ) + +/*************************************************************************** + * GPIO + ***************************************************************************/ + +/* Init the alternate function pins */ + +static __inline__ void gpio_as_ssi (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0xFC00FFFF) | 0x01550000 + +static __inline__ void gpio_as_uart3 (): + GPIO_GPAUR (0) = (GPIO_GPAUR (0) & 0xFFFF0000) | 0x00005555 + +static __inline__ void gpio_as_uart2 (): + GPIO_GPALR (3) = (GPIO_GPALR (3) & 0x3FFFFFFF) | 0x40000000 + GPIO_GPAUR (3) = (PIO_GPAUR (3) & 0xF3FFFFFF) | 0x04000000 + +static __inline__ void gpio_as_uart1 (): + GPIO_GPAUR (0) = (GPIO_GPAUR (0) & 0xFFF0FFFF) | 0x00050000 + +static __inline__ void gpio_as_uart0 (): + GPIO_GPAUR (3) = (GPIO_GPAUR (3) & 0x0FFFFFFF) | 0x50000000 + + +static __inline__ void gpio_as_scc0 (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0xFFFFFFCC) | 0x00000011 + +static __inline__ void gpio_as_scc1 (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0xFFFFFF33) | 0x00000044 + +static __inline__ void gpio_as_scc (): + gpio_as_scc0 () + gpio_as_scc1 () + +static __inline__ void gpio_as_dma (): + GPIO_GPALR (0) = (GPIO_GPALR (0) & 0x00FFFFFF) | 0x55000000 + GPIO_GPAUR (0) = (PIO_GPAUR (0) & 0xFF0FFFFF) | 0x00500000 + +static __inline__ void gpio_as_msc (): + GPIO_GPALR (1) = (GPIO_GPALR (1) & 0xFFFF000F) | 0x00005550 + +static __inline__ void gpio_as_pcmcia (): + GPIO_GPAUR (2) = (GPIO_GPAUR (2) & 0xF000FFFF) | 0x05550000 + +static __inline__ void gpio_as_emc (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0x3FFFFFFF) | 0x40000000 + GPIO_GPAUR (2) = (PIO_GPAUR (2) & 0xFFFF0000) | 0x00005555 + +static __inline__ void gpio_as_lcd_slave (): + GPIO_GPALR (1) = (GPIO_GPALR (1) & 0x0000FFFF) | 0x55550000 + GPIO_GPAUR (1) = (PIO_GPAUR (1) & 0x00000000) | 0x55555555 + +static __inline__ void gpio_as_lcd_master (): + GPIO_GPALR (1) = (GPIO_GPALR (1) & 0x0000FFFF) | 0x55550000 + GPIO_GPAUR (1) = (PIO_GPAUR (1) & 0x00000000) | 0x556A5555 + +static __inline__ void gpio_as_usb (): + GPIO_GPAUR (0) = (GPIO_GPAUR (0) & 0x00FFFFFF) | 0x55000000 + +static __inline__ void gpio_as_ac97 (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0xC3FF03FF) | 0x24005400 + +static __inline__ void gpio_as_i2s_slave (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0xC3FF0CFF) | 0x14005100 + +static __inline__ void gpio_as_i2s_master (): + GPIO_GPALR (2) = (GPIO_GPALR (2) & 0xC3FF0CFF) | 0x28005100 + +static __inline__ void gpio_as_eth (): + GPIO_GPAUR (3) = (GPIO_GPAUR (3) & 0xFC000000) | 0x01555555 + +static __inline__ void gpio_as_pwm (): + GPIO_GPAUR (2) = (GPIO_GPAUR (2) & 0x0FFFFFFF) | 0x50000000 + +static __inline__ void gpio_as_ps2 (): + GPIO_GPALR (1) = (GPIO_GPALR (1) & 0xFFFFFFF0) | 0x00000005 + +static __inline__ void gpio_as_uprt (): + GPIO_GPALR (1) = (GPIO_GPALR (1) & 0x0000000F) | 0x55555550 + GPIO_GPALR (3) = (PIO_GPALR (3) & 0xC0000000) | 0x15555555 + +static __inline__ void gpio_as_cim (): + GPIO_GPALR (0) = (GPIO_GPALR (0) & 0xFF000000) | 0x00555555 + +/*************************************************************************** + * HARB + ***************************************************************************/ + +#define harb_usb0_udc() do { HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; } while (0) + +#define harb_usb0_uhc() do { HARB_HAPOR |= HARB_HAPOR_UCHSEL; } while (0) + +#define harb_set_priority(n) do { HARB_HAPOR = ((HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); } while (0) + +/*************************************************************************** + * I2C + ***************************************************************************/ + +#define i2c_enable() ( I2C_CR |= I2C_CR_I2CE ) +#define i2c_disable() ( I2C_CR &= ~I2C_CR_I2CE ) + +#define i2c_send_start() ( I2C_CR |= I2C_CR_STA ) +#define i2c_send_stop() ( I2C_CR |= I2C_CR_STO ) +#define i2c_send_ack() ( I2C_CR &= ~I2C_CR_AC ) +#define i2c_send_nack() ( I2C_CR |= I2C_CR_AC ) + +#define i2c_set_drf() ( I2C_SR |= I2C_SR_DRF ) +#define i2c_clear_drf() ( I2C_SR &= ~I2C_SR_DRF ) +#define i2c_check_drf() ( I2C_SR & I2C_SR_DRF ) + +#define i2c_received_ack() ( !(I2C_SR & I2C_SR_ACKF) ) +#define i2c_is_busy() ( I2C_SR & I2C_SR_BUSY ) +#define i2c_transmit_ended() ( I2C_SR & I2C_SR_TEND ) + +#define i2c_set_clk(dev_clk, i2c_clk) ( I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) + +#define i2c_read() ( I2C_DR ) +#define i2c_write(val) ( I2C_DR = (val) ) + +/*************************************************************************** + * UDC + ***************************************************************************/ + +#define udc_set_16bit_phy() ( UDC_DevCFGR |= UDC_DevCFGR_PI ) +#define udc_set_8bit_phy() ( UDC_DevCFGR &= ~UDC_DevCFGR_PI ) + +#define udc_enable_sync_frame() ( UDC_DevCFGR |= UDC_DevCFGR_SS ) +#define udc_disable_sync_frame() ( UDC_DevCFGR &= ~UDC_DevCFGR_SS ) + +#define udc_self_powered() ( UDC_DevCFGR |= UDC_DevCFGR_SP ) +#define udc_bus_powered() ( UDC_DevCFGR &= ~UDC_DevCFGR_SP ) + +#define udc_enable_remote_wakeup() ( UDC_DevCFGR |= UDC_DevCFGR_RW ) +#define udc_disable_remote_wakeup() ( UDC_DevCFGR &= ~UDC_DevCFGR_RW ) + +#define udc_set_speed_high() do { UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; } while (0) + +#define udc_set_speed_full() do { UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; } while (0) + +#define udc_set_speed_low() do { UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; } while (0) + + +#define udc_set_dma_mode() ( UDC_DevCR |= UDC_DevCR_DM ) +#define udc_set_slave_mode() ( UDC_DevCR &= ~UDC_DevCR_DM ) +#define udc_set_big_endian() ( UDC_DevCR |= UDC_DevCR_BE ) +#define udc_set_little_endian() ( UDC_DevCR &= ~UDC_DevCR_BE ) +#define udc_generate_resume() ( UDC_DevCR |= UDC_DevCR_RES ) +#define udc_clear_resume() ( UDC_DevCR &= ~UDC_DevCR_RES ) + + +#define udc_get_enumarated_speed() ( UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) +#define udc_suspend_detected() ( UDC_DevSR & UDC_DevSR_SUSP ) +#define udc_get_alternate_setting() ( (UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) +#define udc_get_interface_number() ( (UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) +#define udc_get_config_number() ( (UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) + + +#define udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) +#define udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) +#define udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) +#define udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) +#define udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) + +#define udc_clear_sof() ( UDC_DevIntR |= UDC_DevIntR_SOF ) +#define udc_clear_usb_suspend() ( UDC_DevIntR |= UDC_DevIntR_US ) +#define udc_clear_usb_reset() ( UDC_DevIntR |= UDC_DevIntR_UR ) +#define udc_clear_set_interface() ( UDC_DevIntR |= UDC_DevIntR_SI ) +#define udc_clear_set_config() ( UDC_DevIntR |= UDC_DevIntR_SC ) + +#define udc_mask_sof() ( UDC_DevIntMR |= UDC_DevIntR_SOF ) +#define udc_mask_usb_suspend() ( UDC_DevIntMR |= UDC_DevIntR_US ) +#define udc_mask_usb_reset() ( UDC_DevIntMR |= UDC_DevIntR_UR ) +#define udc_mask_set_interface() ( UDC_DevIntMR |= UDC_DevIntR_SI ) +#define udc_mask_set_config() ( UDC_DevIntMR |= UDC_DevIntR_SC ) +#define udc_mask_all_dev_intrs() ( UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) + +#define udc_unmask_sof() ( UDC_DevIntMR &= ~UDC_DevIntR_SOF ) +#define udc_unmask_usb_suspend() ( UDC_DevIntMR &= ~UDC_DevIntR_US ) +#define udc_unmask_usb_reset() ( UDC_DevIntMR &= ~UDC_DevIntR_UR ) +#define udc_unmask_set_interface() ( UDC_DevIntMR &= ~UDC_DevIntR_SI ) +#define udc_unmask_set_config() ( UDC_DevIntMR &= ~UDC_DevIntR_SC ) +#if 0 +#define udc_unmask_all_dev_intrs() ( UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) +#else +#define udc_unmask_all_dev_intrs() ( UDC_DevIntMR = 0x00000000 ) +#endif + + +#define udc_ep0out_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) +#define udc_ep5out_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) +#define udc_ep6out_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) +#define udc_ep7out_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) + +#define udc_ep0in_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) +#define udc_ep1in_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) +#define udc_ep2in_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) +#define udc_ep3in_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) +#define udc_ep4in_irq_detected(epintr) ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) + + +#define udc_mask_ep0out_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) +#define udc_mask_ep5out_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) +#define udc_mask_ep6out_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) +#define udc_mask_ep7out_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) + +#define udc_unmask_ep0out_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) +#define udc_unmask_ep5out_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) +#define udc_unmask_ep6out_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) +#define udc_unmask_ep7out_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) + +#define udc_mask_ep0in_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) +#define udc_mask_ep1in_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) +#define udc_mask_ep2in_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) +#define udc_mask_ep3in_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) +#define udc_mask_ep4in_irq() ( UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) + +#define udc_unmask_ep0in_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) +#define udc_unmask_ep1in_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) +#define udc_unmask_ep2in_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) +#define udc_unmask_ep3in_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) +#define udc_unmask_ep4in_irq() ( UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) + +#define udc_mask_all_ep_intrs() ( UDC_EPIntMR = 0xffffffff ) +#define udc_unmask_all_ep_intrs() ( UDC_EPIntMR = 0x00000000 ) + + +/* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ +static __inline__ void udc_config_endpoint_type (): + UDC_EP0InCR = (UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL + UDC_EP0OutCR = (UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL + UDC_EP1InCR = (UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR + UDC_EP2InCR = (UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK + UDC_EP3InCR = (UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK + UDC_EP4InCR = (UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO + UDC_EP5OutCR = (UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK + UDC_EP6OutCR = (UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK + UDC_EP7OutCR = (UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO + +#define udc_enable_ep0out_snoop_mode() ( UDC_EP0OutCR |= UDC_EPCR_SN ) +#define udc_enable_ep5out_snoop_mode() ( UDC_EP5OutCR |= UDC_EPCR_SN ) +#define udc_enable_ep6out_snoop_mode() ( UDC_EP6OutCR |= UDC_EPCR_SN ) +#define udc_enable_ep7out_snoop_mode() ( UDC_EP7OutCR |= UDC_EPCR_SN ) + +#define udc_disable_ep0out_snoop_mode() ( UDC_EP0OutCR &= ~UDC_EPCR_SN ) +#define udc_disable_ep5out_snoop_mode() ( UDC_EP5OutCR &= ~UDC_EPCR_SN ) +#define udc_disable_ep6out_snoop_mode() ( UDC_EP6OutCR &= ~UDC_EPCR_SN ) +#define udc_disable_ep7out_snoop_mode() ( UDC_EP7OutCR &= ~UDC_EPCR_SN ) + +#define udc_flush_ep0in_fifo() ( UDC_EP0InCR |= UDC_EPCR_F ) +#define udc_flush_ep1in_fifo() ( UDC_EP1InCR |= UDC_EPCR_F ) +#define udc_flush_ep2in_fifo() ( UDC_EP2InCR |= UDC_EPCR_F ) +#define udc_flush_ep3in_fifo() ( UDC_EP3InCR |= UDC_EPCR_F ) +#define udc_flush_ep4in_fifo() ( UDC_EP4InCR |= UDC_EPCR_F ) + +#define udc_unflush_ep0in_fifo() ( UDC_EP0InCR &= ~UDC_EPCR_F ) +#define udc_unflush_ep1in_fifo() ( UDC_EP1InCR &= ~UDC_EPCR_F ) +#define udc_unflush_ep2in_fifo() ( UDC_EP2InCR &= ~UDC_EPCR_F ) +#define udc_unflush_ep3in_fifo() ( UDC_EP3InCR &= ~UDC_EPCR_F ) +#define udc_unflush_ep4in_fifo() ( UDC_EP4InCR &= ~UDC_EPCR_F ) + +#define udc_enable_ep0in_stall() ( UDC_EP0InCR |= UDC_EPCR_S ) +#define udc_enable_ep0out_stall() ( UDC_EP0OutCR |= UDC_EPCR_S ) +#define udc_enable_ep1in_stall() ( UDC_EP1InCR |= UDC_EPCR_S ) +#define udc_enable_ep2in_stall() ( UDC_EP2InCR |= UDC_EPCR_S ) +#define udc_enable_ep3in_stall() ( UDC_EP3InCR |= UDC_EPCR_S ) +#define udc_enable_ep4in_stall() ( UDC_EP4InCR |= UDC_EPCR_S ) +#define udc_enable_ep5out_stall() ( UDC_EP5OutCR |= UDC_EPCR_S ) +#define udc_enable_ep6out_stall() ( UDC_EP6OutCR |= UDC_EPCR_S ) +#define udc_enable_ep7out_stall() ( UDC_EP7OutCR |= UDC_EPCR_S ) + +#define udc_disable_ep0in_stall() ( UDC_EP0InCR &= ~UDC_EPCR_S ) +#define udc_disable_ep0out_stall() ( UDC_EP0OutCR &= ~UDC_EPCR_S ) +#define udc_disable_ep1in_stall() ( UDC_EP1InCR &= ~UDC_EPCR_S ) +#define udc_disable_ep2in_stall() ( UDC_EP2InCR &= ~UDC_EPCR_S ) +#define udc_disable_ep3in_stall() ( UDC_EP3InCR &= ~UDC_EPCR_S ) +#define udc_disable_ep4in_stall() ( UDC_EP4InCR &= ~UDC_EPCR_S ) +#define udc_disable_ep5out_stall() ( UDC_EP5OutCR &= ~UDC_EPCR_S ) +#define udc_disable_ep6out_stall() ( UDC_EP6OutCR &= ~UDC_EPCR_S ) +#define udc_disable_ep7out_stall() ( UDC_EP7OutCR &= ~UDC_EPCR_S ) + + +#define udc_ep0out_packet_size() ( (UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) +#define udc_ep5out_packet_size() ( (UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) +#define udc_ep6out_packet_size() ( (UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) +#define udc_ep7out_packet_size() ( (UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) + +#define udc_ep0in_received_intoken() ( (UDC_EP0InSR & UDC_EPSR_IN) ) +#define udc_ep1in_received_intoken() ( (UDC_EP1InSR & UDC_EPSR_IN) ) +#define udc_ep2in_received_intoken() ( (UDC_EP2InSR & UDC_EPSR_IN) ) +#define udc_ep3in_received_intoken() ( (UDC_EP3InSR & UDC_EPSR_IN) ) +#define udc_ep4in_received_intoken() ( (UDC_EP4InSR & UDC_EPSR_IN) ) + +#define udc_ep0out_received_none() ( (UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) +#define udc_ep0out_received_data() ( (UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) +#define udc_ep0out_received_setup() ( (UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) + +#define udc_ep5out_received_none() ( (UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) +#define udc_ep5out_received_data() ( (UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) +#define udc_ep5out_received_setup() ( (UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) + +#define udc_ep6out_received_none() ( (UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) +#define udc_ep6out_received_data() ( (UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) +#define udc_ep6out_received_setup() ( (UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) + +#define udc_ep7out_received_none() ( (UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) +#define udc_ep7out_received_data() ( (UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) +#define udc_ep7out_received_setup() ( (UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) + +/* ep7out ISO only */ +#define udc_ep7out_get_pid() ( (UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) + + +#define udc_ep0in_set_buffer_size(n) ( UDC_EP0InBSR = (n) ) +#define udc_ep1in_set_buffer_size(n) ( UDC_EP1InBSR = (n) ) +#define udc_ep2in_set_buffer_size(n) ( UDC_EP2InBSR = (n) ) +#define udc_ep3in_set_buffer_size(n) ( UDC_EP3InBSR = (n) ) +#define udc_ep4in_set_buffer_size(n) ( UDC_EP4InBSR = (n) ) + +#define udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) +#define udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) +#define udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) +#define udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) + + +#define udc_ep0in_set_max_packet_size(n) ( UDC_EP0InMPSR = (n) ) +#define udc_ep0out_set_max_packet_size(n) ( UDC_EP0OutMPSR = (n) ) +#define udc_ep1in_set_max_packet_size(n) ( UDC_EP1InMPSR = (n) ) +#define udc_ep2in_set_max_packet_size(n) ( UDC_EP2InMPSR = (n) ) +#define udc_ep3in_set_max_packet_size(n) ( UDC_EP3InMPSR = (n) ) +#define udc_ep4in_set_max_packet_size(n) ( UDC_EP4InMPSR = (n) ) +#define udc_ep5out_set_max_packet_size(n) ( UDC_EP5OutMPSR = (n) ) +#define udc_ep6out_set_max_packet_size(n) ( UDC_EP6OutMPSR = (n) ) +#define udc_ep7out_set_max_packet_size(n) ( UDC_EP7OutMPSR = (n) ) + +/* set to 0xFFFF for UDC */ +#define udc_set_setup_command_address(n) ( UDC_STCMAR = (n) ) + +/* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) + * c: Configuration number to which this endpoint belongs + * i: Interface number to which this endpoint belongs + * a: Alternate setting to which this endpoint belongs + * p: max Packet size of this endpoint + */ + +static __inline__ void udc_ep0info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL + UDC_EP0InfR &= ~UDC_EPInfR_EPD + UDC_EP0InfR |= UDC_EPInfR_EPD_OUT + UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep1info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP1InfR |= UDC_EPInfR_EPT_INTR + UDC_EP1InfR &= ~UDC_EPInfR_EPD + UDC_EP1InfR |= UDC_EPInfR_EPD_IN + UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep2info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP2InfR |= UDC_EPInfR_EPT_BULK + UDC_EP2InfR &= ~UDC_EPInfR_EPD + UDC_EP2InfR |= UDC_EPInfR_EPD_IN + UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep3info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP3InfR |= UDC_EPInfR_EPT_BULK + UDC_EP3InfR &= ~UDC_EPInfR_EPD + UDC_EP3InfR |= UDC_EPInfR_EPD_IN + UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep4info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP4InfR |= UDC_EPInfR_EPT_ISO + UDC_EP4InfR &= ~UDC_EPInfR_EPD + UDC_EP4InfR |= UDC_EPInfR_EPD_IN + UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep5info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP5InfR |= UDC_EPInfR_EPT_BULK + UDC_EP5InfR &= ~UDC_EPInfR_EPD + UDC_EP5InfR |= UDC_EPInfR_EPD_OU; + UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep6info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP6InfR |= UDC_EPInfR_EPT_BULK + UDC_EP6InfR &= ~UDC_EPInfR_EPD + UDC_EP6InfR |= UDC_EPInfR_EPD_OU; + UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT) + +static __inline__ void udc_ep7info_init (unsigned c, unsigned i, unsigned a, unsigned p): + UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK + UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT) + UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK + UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT) + UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK + UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT) + UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK + UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT) + UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK + UDC_EP7InfR |= UDC_EPInfR_EPT_ISO + UDC_EP7InfR &= ~UDC_EPInfR_EPD + UDC_EP7InfR |= UDC_EPInfR_EPD_OU; + UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK + UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT) + + +/*************************************************************************** + * DMAC + ***************************************************************************/ + +/* n is the DMA channel (0 - 7) */ + +#define dmac_enable_all_channels() ( DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) +#define dmac_disable_all_channels() ( DMAC_DMACR &= ~DMAC_DMACR_DME ) + +/* p=0,1,2,3 */ +#define dmac_set_priority(p) ( DMAC_DMACR = (DMAC_DMACR & ~DMAC_DMACR_PR_MASK) | ((p) << DMAC_DMACR_PR_BIT) ) + +#define dmac_test_halt_error() ( DMAC_DMACR & DMAC_DMACR_HTR ) +#define dmac_test_addr_error() ( DMAC_DMACR & DMAC_DMACR_AER ) + +#define dmac_enable_channel(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) +#define dmac_disable_channel(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) +#define dmac_channel_enabled(n) ( DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) + +#define dmac_channel_enable_irq(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) +#define dmac_channel_disable_irq(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) + +#define dmac_channel_transmit_halt_detected(n) ( DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) +#define dmac_channel_transmit_end_detected(n) ( DMAC_DCCSR(n) & DMAC_DCCSR_TC ) +#define dmac_channel_address_error_detected(n) ( DMAC_DCCSR(n) & DMAC_DCCSR_AR ) + +#define dmac_channel_clear_transmit_halt(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) +#define dmac_channel_clear_transmit_end(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) +#define dmac_channel_clear_address_error(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) + +#define dmac_channel_set_single_mode(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) +#define dmac_channel_set_block_mode(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) + +#define dmac_channel_set_transfer_unit_32bit(n) (DMAC_DCCSR (n) = (DMAC_DCCSR & ~DMAC_DCCSR_DS_MASK) | DMAC_DCCSR_DS_32b) + +#define dmac_channel_set_transfer_unit_16bit(n) (DMAC_DCCSR(n) = (DMAC_DCCSR(n) & ~DMAC_DCCSR_DS_MASK) | DMAC_DCCSR_DS_16b) + +#define dmac_channel_set_transfer_unit_8bit(n) (DMAC_DCCSR(n) = (DMAC_DCCSR(n) & ~DMAC_DCCSR_DS_MASK) | DMAC_DCCSR_DS_8b) + +#define dmac_channel_set_transfer_unit_16byte(n) (DMAC_DCCSR(n) = (DMAC_DCCSR(n) & ~DMAC_DCCSR_DS_MASK) | DMAC_DCCSR_DS_16B) + +#define dmac_channel_set_transfer_unit_32byte(n) (DMAC_DCCSR(n) = (DMAC_DCCSR(n) & ~DMAC_DCCSR_DS_MASK) | DMAC_DCCSR_DS_32B) + +/* w=8,16,32 */ +#define dmac_channel_set_dest_port_width(n,w) (DMAC_DCCSR(n) = (MAC_DCCSR(n) & ~DMAC_DCCSR_DWDH_MASK) | DMAC_DCCSR_DWDH_##w) + +/* w=8,16,32 */ +#define dmac_channel_set_src_port_width(n,w) (DMAC_DCCSR(n) = (MAC_DCCSR(n) & ~DMAC_DCCSR_SWDH_MASK) | DMAC_DCCSR_SWDH_##w) + +/* v=0-15 */ +#define dmac_channel_set_rdil(n,v) (DMAC_DCCSR(n) = (MAC_DCCSR(n) & ~DMAC_DCCSR_RDIL_MASK) | ((v) << DMAC_DCCSR_RDIL_BIT)) + +#define dmac_channel_dest_addr_fixed(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) +#define dmac_channel_dest_addr_increment(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) + +#define dmac_channel_src_addr_fixed(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) +#define dmac_channel_src_addr_increment(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) + +#define dmac_channel_set_eop_high(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) +#define dmac_channel_set_eop_low(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) + +#define dmac_channel_set_erdm(n,m) (DMAC_DCCSR(n) = (MAC_DCCSR(n) & ~DMAC_DCCSR_SWDH_MASK;) | ((m) << DMAC_DCCSR_ERDM_BIT)) + +#define dmac_channel_set_eackm(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) +#define dmac_channel_clear_eackm(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) + +#define dmac_channel_set_eacks(n) ( DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) +#define dmac_channel_clear_eacks(n) ( DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) + + +#define dmac_channel_irq_detected(n) ( DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) + +static __inline__ int dmac_get_irq (): + int i + for i = 0; i < NUM_DMA; i++: + if dmac_channel_irq_detected(i): + return i + return -1 + +/*************************************************************************** + * AIC (AC'97 & I2S Controller) + ***************************************************************************/ + +#define aic_enable() ( AIC_FR |= AIC_FR_ENB ) +#define aic_disable() ( AIC_FR &= ~AIC_FR_ENB ) +#define aic_reset() ( AIC_FR |= AIC_FR_RST ) +#define aic_select_ac97() ( AIC_FR &= ~AIC_FR_AUSEL ) +#define aic_select_i2s() ( AIC_FR |= AIC_FR_AUSEL ) + +#define i2s_as_master() ( AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) +#define i2s_as_slave() ( AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) + +#define aic_set_transmit_trigger(n) (AIC_FR = (IC_FR & ~AIC_FR_TFTH_MASK;) | ((n) << AIC_FR_TFTH_BIT)) + +#define aic_set_receive_trigger(n) (AIC_FR = (IC_FR & ~AIC_FR_RFTH_MASK;) | ((n) << AIC_FR_RFTH_BIT)) + +#define aic_enable_record() ( AIC_CR |= AIC_CR_EREC ) +#define aic_disable_record() ( AIC_CR &= ~AIC_CR_EREC ) +#define aic_enable_replay() ( AIC_CR |= AIC_CR_ERPL ) +#define aic_disable_replay() ( AIC_CR &= ~AIC_CR_ERPL ) +#define aic_enable_loopback() ( AIC_CR |= AIC_CR_ENLBF ) +#define aic_disable_loopback() ( AIC_CR &= ~AIC_CR_ENLBF ) + +#define aic_flush_fifo() ( AIC_CR |= AIC_CR_FLUSH ) +#define aic_unflush_fifo() ( AIC_CR &= ~AIC_CR_FLUSH ) + +#define aic_enable_transmit_intr() ( AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) +#define aic_disable_transmit_intr() ( AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) +#define aic_enable_receive_intr() ( AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) +#define aic_disable_receive_intr() ( AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) + +#define aic_enable_transmit_dma() ( AIC_CR |= AIC_CR_TDMS ) +#define aic_disable_transmit_dma() ( AIC_CR &= ~AIC_CR_TDMS ) +#define aic_enable_receive_dma() ( AIC_CR |= AIC_CR_RDMS ) +#define aic_disable_receive_dma() ( AIC_CR &= ~AIC_CR_RDMS ) + +#define aic_enable_mono2stereo() +#define aic_disable_mono2stereo() +#define aic_enable_byteswap() +#define aic_disable_byteswap() +#define aic_enable_unsignadj() +#define aic_disable_unsignadj() + +#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 +#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 +#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 +#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 +#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 +#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 + +#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 +#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 +#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 +#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 +#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 +#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 + +#define ac97_set_xs_none() ( AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) +#define ac97_set_xs_mono() (AIC_ACCR1 = (AIC_ACCR1 & ~AIC_ACCR1_XS_MASK) | AC97_PCM_XS_R_FRONT) +#define ac97_set_xs_stereo() (AIC_ACCR1 = (AIC_ACCR1 & ~AIC_ACCR1_XS_MASK | AC97_PCM_XS_L_FRONT) | AC97_PCM_XS_R_FRONT) + +/* In fact, only stereo is support now. */ +#define ac97_set_rs_none() ( AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) +#define ac97_set_rs_mono() (AIC_ACCR1 = (AIC_ACCR1 & ~AIC_ACCR1_RS_MASK) | AC97_PCM_RS_R_FRONT) +#define ac97_set_rs_stereo() (AIC_ACCR1 = (AIC_ACCR1 & ~AIC_ACCR1_RS_MASK | AC97_PCM_RS_L_FRONT) | AC97_PCM_RS_R_FRONT) + +static __inline__ void ac97_warm_reset_codec (): + AIC_ACCR2 |= AIC_ACCR2_SA + AIC_ACCR2 |= AIC_ACCR2_SS + udelay(1) + AIC_ACCR2 &= ~AIC_ACCR2_SS + AIC_ACCR2 &= ~AIC_ACCR2_SA + +#define Jz_AC97_RESET_BUG 1 + +#ifndef Jz_AC97_RESET_BUG +static __inline__ void ac97_cold_reset_codec (): + AIC_ACCR2 |= AIC_ACCR2_SA + AIC_ACCR2 &= ~AIC_ACCR2_SS + AIC_ACCR2 |= AIC_ACCR2_SR + udelay(1) + AIC_ACCR2 &= ~AIC_ACCR2_SR + AIC_ACCR2 &= ~AIC_ACCR2_SA +#else +static __inline__ ac97_cold_reset_codec (): + //gpio_as_output(70); /* SDATA_OUT */ + //gpio_as_output(71); /* SDATA_IN */ + //gpio_as_output(78); /* SYNC */ + //gpio_as_output(69); /* RESET# */ + GPIO_GPDIR (2) |= 0x000040e0 + GPIO_GPDR (2) &= ~0x000040e0 + udelay (10) + GPIO_GPDR (2) |= 0x00000020 + udelay (1) + gpio_as_ac97 () +#endif + +/* n=8,16,18,20 */ +#define ac97_set_iass(n) ( AIC_ACCR2 = (AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) +#define ac97_set_oass(n) ( AIC_ACCR2 = (AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) + +#define i2s_select_i2s() ( AIC_I2SCR &= ~AIC_I2SCR_AMSL ) +#define i2s_select_left_justified() ( AIC_I2SCR |= AIC_I2SCR_AMSL ) + +/* n=8,16,18,20,24 */ +#define i2s_set_sample_size(n) ( AIC_I2SCR = (AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT ) + +#define i2s_stop_clock() ( AIC_I2SCR |= AIC_I2SCR_STPBK ) +#define i2s_start_clock() ( AIC_I2SCR &= ~AIC_I2SCR_STPBK ) + +#define aic_transmit_request() ( AIC_SR & AIC_SR_TFS ) +#define aic_receive_request() ( AIC_SR & AIC_SR_RFS ) +#define aic_transmit_underrun() ( AIC_SR & AIC_SR_TUR ) +#define aic_receive_overrun() ( AIC_SR & AIC_SR_ROR ) + +#define aic_clear_errors() ( AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) + +#define aic_get_transmit_resident() ( (AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) +#define aic_get_receive_count() ( (AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) + +#define ac97_command_transmitted() ( AIC_ACSR & AIC_ACSR_CADT ) +#define ac97_status_received() ( AIC_ACSR & AIC_ACSR_SADR ) +#define ac97_status_receive_timeout() ( AIC_ACSR & AIC_ACSR_RSTO ) +#define ac97_codec_is_low_power_mode() ( AIC_ACSR & AIC_ACSR_CLPM ) +#define ac97_codec_is_ready() ( AIC_ACSR & AIC_ACSR_CRDY ) + +#define i2s_is_busy() ( AIC_I2SSR & AIC_I2SSR_BSY ) + +#define CODEC_READ_CMD (1 << 19) +#define CODEC_WRITE_CMD (0 << 19) +#define CODEC_INDEX_BIT 12 +#define CODEC_INDEX_MASK (0x7f << CODEC_INDEX_BIT) /* 18:12 */ +#define CODEC_DATA_BIT 4 +#define CODEC_DATA_MASK (0x0ffff << 4) /* 19:4 */ + +#define ac97_out_rcmd_addr(reg) ( AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_INDEX_BIT) ) + +#define ac97_out_wcmd_addr(reg) ( AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_INDEX_BIT) ) + +#define ac97_out_data(value) ( AIC_ACCDR = ((value) << CODEC_DATA_BIT) ) + +#define ac97_in_data() ( (AIC_ACSDR & CODEC_DATA_MASK) >> CODEC_DATA_BIT ) + +#define ac97_in_status_addr() ( (AIC_ACSAR & CODEC_INDEX_MASK) >> CODEC_INDEX_BIT ) + +#define i2s_set_sample_rate(i2sclk, sync) ( AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) + +#define aic_write_tfifo(v) ( AIC_DR = (v) ) +#define aic_read_rfifo() ( AIC_DR ) + +// +// Define next ops for AC97 compatible +// + +#define AC97_ACSR AIC_ACSR + +#define ac97_enable() aic_enable(); aic_select_ac97() +#define ac97_disable() aic_disable() +#define ac97_reset() aic_reset() + +#define ac97_set_transmit_trigger(n) aic_set_transmit_trigger(n) +#define ac97_set_receive_trigger(n) aic_set_receive_trigger(n) + +#define ac97_enable_record() aic_enable_record() +#define ac97_disable_record() aic_disable_record() +#define ac97_enable_replay() aic_enable_replay() +#define ac97_disable_replay() aic_disable_replay() +#define ac97_enable_loopback() aic_enable_loopback() +#define ac97_disable_loopback() aic_disable_loopback() + +#define ac97_enable_transmit_dma() aic_enable_transmit_dma() +#define ac97_disable_transmit_dma() aic_disable_transmit_dma() +#define ac97_enable_receive_dma() aic_enable_receive_dma() +#define ac97_disable_receive_dma() aic_disable_receive_dma() + +#define ac97_transmit_request() aic_transmit_request() +#define ac97_receive_request() aic_receive_request() +#define ac97_transmit_underrun() aic_transmit_underrun() +#define ac97_receive_overrun() aic_receive_overrun() + +#define ac97_clear_errors() aic_clear_errors() + +#define ac97_get_transmit_resident() aic_get_transmit_resident() +#define ac97_get_receive_count() aic_get_receive_count() + +#define ac97_enable_transmit_intr() aic_enable_transmit_intr() +#define ac97_disable_transmit_intr() aic_disable_transmit_intr() +#define ac97_enable_receive_intr() aic_enable_receive_intr() +#define ac97_disable_receive_intr() aic_disable_receive_intr() + +#define ac97_write_tfifo(v) aic_write_tfifo(v) +#define ac97_read_rfifo() aic_read_rfifo() + +// +// Define next ops for I2S compatible +// + +#define I2S_ACSR AIC_I2SSR + +#define i2s_enable() aic_enable(); aic_select_i2s() +#define i2s_disable() aic_disable() +#define i2s_reset() aic_reset() + +#define i2s_set_transmit_trigger(n) aic_set_transmit_trigger(n) +#define i2s_set_receive_trigger(n) aic_set_receive_trigger(n) + +#define i2s_enable_record() aic_enable_record() +#define i2s_disable_record() aic_disable_record() +#define i2s_enable_replay() aic_enable_replay() +#define i2s_disable_replay() aic_disable_replay() +#define i2s_enable_loopback() aic_enable_loopback() +#define i2s_disable_loopback() aic_disable_loopback() + +#define i2s_enable_transmit_dma() aic_enable_transmit_dma() +#define i2s_disable_transmit_dma() aic_disable_transmit_dma() +#define i2s_enable_receive_dma() aic_enable_receive_dma() +#define i2s_disable_receive_dma() aic_disable_receive_dma() + +#define i2s_transmit_request() aic_transmit_request() +#define i2s_receive_request() aic_receive_request() +#define i2s_transmit_underrun() aic_transmit_underrun() +#define i2s_receive_overrun() aic_receive_overrun() + +#define i2s_clear_errors() aic_clear_errors() + +#define i2s_get_transmit_resident() aic_get_transmit_resident() +#define i2s_get_receive_count() aic_get_receive_count() + +#define i2s_enable_transmit_intr() aic_enable_transmit_intr() +#define i2s_disable_transmit_intr() aic_disable_transmit_intr() +#define i2s_enable_receive_intr() aic_enable_receive_intr() +#define i2s_disable_receive_intr() aic_disable_receive_intr() + +#define i2s_write_tfifo(v) aic_write_tfifo(v) +#define i2s_read_rfifo() aic_read_rfifo() + +static __inline__ void i2s_reset_codec (): + //gpio_as_output(70); /* SDATA_OUT */ + //gpio_as_output(71); /* SDATA_IN */ + //gpio_as_output(78); /* SYNC */ + //gpio_as_output(69); /* RESET# */ + GPIO_GPDIR (2) |= 0x000040e0 + GPIO_GPDR (2) &= ~0x000040e0 + gpio_as_i2s_master() + + +/*************************************************************************** + * LCD + ***************************************************************************/ + +#define lcd_set_dis() ( LCD_CTRL |= LCD_CTRL_DIS ) +#define lcd_clr_dis() ( LCD_CTRL &= ~LCD_CTRL_DIS ) + +#define lcd_set_ena() ( LCD_CTRL |= LCD_CTRL_ENA ) +#define lcd_clr_ena() ( LCD_CTRL &= ~LCD_CTRL_ENA ) + +/* n=1,2,4,8,16 */ +#define lcd_set_bpp(n) ( LCD_CTRL = (LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) + +/* n=4,8,16 */ +#define lcd_set_burst_length(n) (LCD_CTRL = (LCD_CTRL & ~LCD_CTRL_BST_MASK) | LCD_CTRL_BST_n##) + +#define lcd_select_rgb565() ( LCD_CTRL &= ~LCD_CTRL_RGB555 ) +#define lcd_select_rgb555() ( LCD_CTRL |= LCD_CTRL_RGB555 ) + +#define lcd_set_ofup() ( LCD_CTRL |= LCD_CTRL_OFUP ) +#define lcd_clr_ofup() ( LCD_CTRL &= ~LCD_CTRL_OFUP ) + +/* n=2,4,16 */ +#define lcd_set_stn_frc(n) (LCD_CTRL = (LCD_CTRL & ~LCD_CTRL_FRC_MASK) | LCD_CTRL_FRC_n##) + + +#define lcd_pixel_endian_little() ( LCD_CTRL |= LCD_CTRL_PEDN ) +#define lcd_pixel_endian_big() ( LCD_CTRL &= ~LCD_CTRL_PEDN ) + +#define lcd_reverse_byte_endian() ( LCD_CTRL |= LCD_CTRL_BEDN ) +#define lcd_normal_byte_endian() ( LCD_CTRL &= ~LCD_CTRL_BEDN ) + +#define lcd_enable_eof_intr() ( LCD_CTRL |= LCD_CTRL_EOFM ) +#define lcd_disable_eof_intr() ( LCD_CTRL &= ~LCD_CTRL_EOFM ) + +#define lcd_enable_sof_intr() ( LCD_CTRL |= LCD_CTRL_SOFM ) +#define lcd_disable_sof_intr() ( LCD_CTRL &= ~LCD_CTRL_SOFM ) + +#define lcd_enable_ofu_intr() ( LCD_CTRL |= LCD_CTRL_OFUM ) +#define lcd_disable_ofu_intr() ( LCD_CTRL &= ~LCD_CTRL_OFUM ) + +#define lcd_enable_ifu0_intr() ( LCD_CTRL |= LCD_CTRL_IFUM0 ) +#define lcd_disable_ifu0_intr() ( LCD_CTRL &= ~LCD_CTRL_IFUM0 ) + +#define lcd_enable_ifu1_intr() ( LCD_CTRL |= LCD_CTRL_IFUM1 ) +#define lcd_disable_ifu1_intr() ( LCD_CTRL &= ~LCD_CTRL_IFUM1 ) + +#define lcd_enable_ldd_intr() ( LCD_CTRL |= LCD_CTRL_LDDM ) +#define lcd_disable_ldd_intr() ( LCD_CTRL &= ~LCD_CTRL_LDDM ) + +#define lcd_enable_qd_intr() ( LCD_CTRL |= LCD_CTRL_QDM ) +#define lcd_disable_qd_intr() ( LCD_CTRL &= ~LCD_CTRL_QDM ) + + +/* LCD status register indication */ + +#define lcd_quick_disable_done() ( LCD_STATE & LCD_STATE_QD ) +#define lcd_disable_done() ( LCD_STATE & LCD_STATE_LDD ) +#define lcd_infifo0_underrun() ( LCD_STATE & LCD_STATE_IFU0 ) +#define lcd_infifo1_underrun() ( LCD_STATE & LCD_STATE_IFU1 ) +#define lcd_outfifo_underrun() ( LCD_STATE & LCD_STATE_OFU ) +#define lcd_start_of_frame() ( LCD_STATE & LCD_STATE_SOF ) +#define lcd_end_of_frame() ( LCD_STATE & LCD_STATE_EOF ) + +#define lcd_clr_outfifounderrun() ( LCD_STATE &= ~LCD_STATE_OFU ) +#define lcd_clr_sof() ( LCD_STATE &= ~LCD_STATE_SOF ) +#define lcd_clr_eof() ( LCD_STATE &= ~LCD_STATE_EOF ) + +#define lcd_panel_white() ( LCD_DEV |= LCD_DEV_WHITE ) +#define lcd_panel_black() ( LCD_DEV &= ~LCD_DEV_WHITE ) + +/* n=1,2,4,8 for single mono-STN + * n=4,8 for dual mono-STN + */ +#define lcd_set_panel_datawidth(n) (LCD_DEV = (LCD_DEV & ~LCD_DEV_PDW_MASK) | LCD_DEV_PDW_n##) + +/* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */ +#define lcd_set_panel_mode(m) (LCD_DEV = (LCD_DEV & ~LCD_DEV_MODE_MASK) | (m)) + +/* n = 0-255 */ +#define lcd_disable_ac_bias() ( LCD_IO = 0xff ) +#define lcd_set_ac_bias(n) (LCD_IO = (LCD_IO & ~LCD_IO_ACB_MASK) | ((n) << LCD_IO_ACB_BIT)) + +#define lcd_io_set_dir() ( LCD_IO |= LCD_IO_DIR ) +#define lcd_io_clr_dir() ( LCD_IO &= ~LCD_IO_DIR ) + +#define lcd_io_set_dep() ( LCD_IO |= LCD_IO_DEP ) +#define lcd_io_clr_dep() ( LCD_IO &= ~LCD_IO_DEP ) + +#define lcd_io_set_vsp() ( LCD_IO |= LCD_IO_VSP ) +#define lcd_io_clr_vsp() ( LCD_IO &= ~LCD_IO_VSP ) + +#define lcd_io_set_hsp() ( LCD_IO |= LCD_IO_HSP ) +#define lcd_io_clr_hsp() ( LCD_IO &= ~LCD_IO_HSP ) + +#define lcd_io_set_pcp() ( LCD_IO |= LCD_IO_PCP ) +#define lcd_io_clr_pcp() ( LCD_IO &= ~LCD_IO_PCP ) + +#define lcd_vsync_get_vps() ( (LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) + +#define lcd_vsync_get_vpe() ( (LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) +#define lcd_vsync_set_vpe(n) (LCD_VSYNC = (LCD_VSYNC & ~LCD_VSYNC_VPE_MASK) | (n) << LCD_VSYNC_VPE_BIT) + +#define lcd_hsync_get_hps() ( (LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) +#define lcd_hsync_set_hps(n) (LCD_HSYNC = (LCD_HSYNC & ~LCD_HSYNC_HPS_MASK) | (n) << LCD_HSYNC_HPS_BIT) + +#define lcd_hsync_get_hpe() ( (LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) +#define lcd_hsync_set_hpe(n) (LCD_HSYNC = (LCD_HSYNC & ~LCD_HSYNC_HPE_MASK) | (n) << LCD_HSYNC_HPE_BIT) + +#define lcd_vat_get_ht() ( (LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) +#define lcd_vat_set_ht(n) (LCD_VAT = (LCD_VAT & ~LCD_VAT_HT_MASK) | (n) << LCD_VAT_HT_BIT) + +#define lcd_vat_get_vt() ( (LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) +#define lcd_vat_set_vt(n) (LCD_VAT = (LCD_VAT & ~LCD_VAT_VT_MASK) | (n) << LCD_VAT_VT_BIT) + +#define lcd_dah_get_hds() ( (LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) +#define lcd_dah_set_hds(n) (LCD_DAH = (LCD_DAH & ~LCD_DAH_HDS_MASK) | (n) << LCD_DAH_HDS_BIT) + +#define lcd_dah_get_hde() ( (LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) +#define lcd_dah_set_hde(n) (LCD_DAH = (LCD_DAH & ~LCD_DAH_HDE_MASK) | (n) << LCD_DAH_HDE_BIT) + +#define lcd_dav_get_vds() ( (LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) +#define lcd_dav_set_vds(n) (LCD_DAV = (LCD_DAV & ~LCD_DAV_VDS_MASK) | (n) << LCD_DAV_VDS_BIT) + +#define lcd_dav_get_vde() ( (LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) +#define lcd_dav_set_vde(n) (LCD_DAV = (LCD_DAV & ~LCD_DAV_VDE_MASK) | (n) << LCD_DAV_VDE_BIT) + +#define lcd_cmd0_set_sofint() ( LCD_CMD0 |= LCD_CMD_SOFINT ) +#define lcd_cmd0_clr_sofint() ( LCD_CMD0 &= ~LCD_CMD_SOFINT ) +#define lcd_cmd1_set_sofint() ( LCD_CMD1 |= LCD_CMD_SOFINT ) +#define lcd_cmd1_clr_sofint() ( LCD_CMD1 &= ~LCD_CMD_SOFINT ) + +#define lcd_cmd0_set_eofint() ( LCD_CMD0 |= LCD_CMD_EOFINT ) +#define lcd_cmd0_clr_eofint() ( LCD_CMD0 &= ~LCD_CMD_EOFINT ) +#define lcd_cmd1_set_eofint() ( LCD_CMD1 |= LCD_CMD_EOFINT ) +#define lcd_cmd1_clr_eofint() ( LCD_CMD1 &= ~LCD_CMD_EOFINT ) + +#define lcd_cmd0_set_pal() ( LCD_CMD0 |= LCD_CMD_PAL ) +#define lcd_cmd0_clr_pal() ( LCD_CMD0 &= ~LCD_CMD_PAL ) + +#define lcd_cmd0_get_len() ( (LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) +#define lcd_cmd1_get_len() ( (LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) + + + +/*************************************************************************** + * DES + ***************************************************************************/ + + +/*************************************************************************** + * CPM + ***************************************************************************/ +#define cpm_plcr1_fd() ((CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT) +#define cpm_plcr1_rd() ((CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT) +#define cpm_plcr1_od() ((CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT) +#define cpm_cfcr_mfr() ((CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT) +#define cpm_cfcr_pfr() ((CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT) +#define cpm_cfcr_sfr() ((CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT) +#define cpm_cfcr_ifr() ((CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT) + +static __inline__ unsigned int cpm_divisor_encode(unsigned int n) +{ + unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32}; + int i; + for (i=0;i<10;i++) + if (n < encode[i]) + break; + return i; +} + +#define cpm_set_mclk_div(n) ( CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_MFR_MASK) | ((n) << (CPM_CFCR_MFR_BIT)) ) + +#define cpm_set_pclk_div(n) ( CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_PFR_MASK) | ((n) << (CPM_CFCR_PFR_BIT)) ) + +#define cpm_set_sclk_div(n) ( CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_SFR_MASK) | ((n) << (CPM_CFCR_SFR_BIT)) ) + +#define cpm_set_iclk_div(n) ( CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_IFR_MASK) | ((n) << (CPM_CFCR_IFR_BIT)) ) + +#define cpm_set_lcdclk_div(n) ( CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_LFR_MASK) | ((n) << (CPM_CFCR_LFR_BIT)) ) + +#define cpm_enable_cko1() (CPM_CFCR |= CPM_CFCR_CKOEN1) +#define cpm_enable_cko2() (CPM_CFCR |= CPM_CFCR_CKOEN2) +#define cpm_disable_cko1() (CPM_CFCR &= ~CPM_CFCR_CKOEN1) +#define cpm_disable_cko2() (CPM_CFCR &= ~CPM_CFCR_CKOEN2) + +static __inline__ void cpm_select_msc_clk (bool type): + if type == 0: + CPM_CFCR &= ~CPM_CFCR_MSC + else: + CPM_CFCR |= CPM_CFCR_MSC + CPM_CFCR |= CPM_CFCR_UPE + +#define cpm_idle_mode() ( (CPM_LPCR = (CPM_LPCR & ~CPM_LPCR_LPM_MASK) | CPM_LPCR_LPM_IDLE) ) +#define cpm_sleep_mode() ( (CPM_LPCR = (CPM_LPCR & ~CPM_LPCR_LPM_MASK) | CPM_LPCR_LPM_SLEEP) ) +#define cpm_hibernate_mode() (CPM_LPCR = (CPM_LPCR & ~CPM_LPCR_LPM_MASK) | CPM_LPCR_LPM_HIBERNATE) + +#define cpm_start_uart0() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART0)) +#define cpm_start_uart1() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART1)) +#define cpm_start_uart2() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART2)) +#define cpm_start_uart3() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART3)) +#define cpm_start_ost() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_OST)) +#define cpm_start_dmac() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_DMAC)) +#define cpm_start_uhc() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UHC)) +#define cpm_start_lcd() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_LCD)) +#define cpm_start_i2c() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_I2C)) +#define cpm_start_aic_pclk() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICPCLK)) +#define cpm_start_aic_bitclk() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICBCLK)) +#define cpm_start_pwm0() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM0)) +#define cpm_start_pwm1() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM1)) +#define cpm_start_ssi() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SSI)) +#define cpm_start_msc() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_MSC)) +#define cpm_start_scc() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SCC)) +#define cpm_start_eth() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_ETH)) +#define cpm_start_kbc() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_KBC)) +#define cpm_start_cim() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_CIM)) +#define cpm_start_udc() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UDC)) +#define cpm_start_uprt() (CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UPRT)) +#define cpm_start_all() (CPM_MSCR = 0) +#define cpm_stop_uart0() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART0)) +#define cpm_stop_uart1() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART1)) +#define cpm_stop_uart2() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART2)) +#define cpm_stop_uart3() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART3)) +#define cpm_stop_ost() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_OST)) +#define cpm_stop_dmac() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_DMAC)) +#define cpm_stop_uhc() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UHC)) +#define cpm_stop_lcd() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_LCD)) +#define cpm_stop_i2c() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_I2C)) +#define cpm_stop_aic_pclk() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICPCLK)) +#define cpm_stop_aic_bitclk() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICBCLK)) +#define cpm_stop_pwm0() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM0)) +#define cpm_stop_pwm1() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM1)) +#define cpm_stop_ssi() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_SSI)) +#define cpm_stop_msc() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_MSC)) +#define cpm_stop_scc() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_SCC)) +#define cpm_stop_eth() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_ETH)) +#define cpm_stop_kbc() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_KBC)) +#define cpm_stop_cim() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_CIM)) +#define cpm_stop_udc() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UDC)) +#define cpm_stop_uprt() (CPM_MSCR |= (1 << CPM_MSCR_MSTP_UPRT)) +#define cpm_stop_all() (CPM_MSCR = 0xffffffff) + + +/*************************************************************************** + * SSI + ***************************************************************************/ + +#define ssi_enable() ( SSI_CR0 |= SSI_CR0_SSIE ) +#define ssi_disable() ( SSI_CR0 &= ~SSI_CR0_SSIE ) +#define ssi_select_ce() ( SSI_CR0 &= ~SSI_CR0_FSEL ) + +#define ssi_normal_mode() ( SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) + +#define ssi_select_ce2() (SSI_CR1 = (SSI_CR0 & ~SSI_CR1_MULTS) | SSI_CR0_FSEL) + +#define ssi_select_gpc() (SSI_CR0 = (SSI_CR1 & ~SSI_CR0_FSEL) | SSI_CR1_MULTS) + +#define ssi_enable_tx_intr() ( SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) + +#define ssi_disable_tx_intr() ( SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) + +#define ssi_enable_rx_intr() ( SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) + +#define ssi_disable_rx_intr() ( SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) + +#define ssi_enable_loopback() ( SSI_CR0 |= SSI_CR0_LOOP ) +#define ssi_disable_loopback() ( SSI_CR0 &= ~SSI_CR0_LOOP ) + +#define ssi_enable_receive() ( SSI_CR0 &= ~SSI_CR0_DISREV ) +#define ssi_disable_receive() ( SSI_CR0 |= SSI_CR0_DISREV ) + +#define ssi_finish_receive() ( SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) + +#define ssi_disable_recvfinish() ( SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) + +#define ssi_flush_txfifo() ( SSI_CR0 |= SSI_CR0_TFLUSH ) +#define ssi_flush_rxfifo() ( SSI_CR0 |= SSI_CR0_RFLUSH ) + +#define ssi_flush_fifo() ( SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) + +#define ssi_finish_transmit() ( SSI_CR1 &= ~SSI_CR1_UNFIN ) + +static __inline__ void ssi_spi_format (): + SSI_CR1 &= ~SSI_CR1_FMAT_MASK + SSI_CR1 |= SSI_CR1_FMAT_SPI + SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK) + SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1) + +/* TI's SSP format, must clear SSI_CR1.UNFIN */ +#define ssi_ssp_format() SSI_CR1 = (SSI_CR1 & ~(SSI_CR1_FMAT_MASK |SSI_CR1_UNFIN)) (|= SSI_CR1_FMAT_SSP) + +/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ +static __inline__ void ssi_microwire_format (): + SSI_CR1 &= ~SSI_CR1_FMAT_MASK + SSI_CR1 |= SSI_CR1_FMAT_MW1 + SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK) + SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3) + SSI_CR0 &= ~SSI_CR0_RFINE + +/* CE# level (FRMHL), CE# in interval time (ITFRM), + clock phase and polarity (PHA POL), + interval time (SSIITR), interval characters/frame (SSIICR) */ + + /* frmhl,endian,mcom,flen,pha,pol MASK */ +#define SSICR1_MISC_MASK ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) + +#define ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) do { SSI_CR1 &= ~SSICR1_MISC_MASK; SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | ((pha) << 1) | (pol); } while(0) + +/* Transfer with MSB or LSB first */ +#define ssi_set_msb() ( SSI_CR1 &= ~SSI_CR1_LFST ) +#define ssi_set_lsb() ( SSI_CR1 |= SSI_CR1_LFST ) + +#define ssi_set_frame_length(n) ( SSI_CR1 = (SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) ) + +/* n = 1 - 16 */ +#define ssi_set_microwire_command_length(n) ( SSI_CR1 = ((SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) + +/* Set the clock phase for SPI */ +#define ssi_set_spi_clock_phase(n) ( SSI_CR1 = ((SSI_CR1 & ~SSI_CR1_PHA) | ((n&0x1) << 1))) + +/* Set the clock polarity for SPI */ +#define ssi_set_spi_clock_polarity(n) ( SSI_CR1 = ((SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) + +/* n = 1,4,8,14 */ +#define ssi_set_tx_trigger(n) do { SSI_CR1 &= ~SSI_CR1_TTRG_MASK; SSI_CR1 |= SSI_CR1_TTRG_##n; } while (0) + +/* n = 1,4,8,14 */ +#define ssi_set_rx_trigger(n) do { SSI_CR1 &= ~SSI_CR1_RTRG_MASK; SSI_CR1 |= SSI_CR1_RTRG_##n; } while (0) + +#define ssi_get_txfifo_count() ( (SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) + +#define ssi_get_rxfifo_count() ( (SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) + +#define ssi_clear_errors() ( SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) + +#define ssi_transfer_end() ( SSI_SR & SSI_SR_END ) +#define ssi_is_busy() ( SSI_SR & SSI_SR_BUSY ) + +#define ssi_txfifo_full() ( SSI_SR & SSI_SR_TFF ) +#define ssi_rxfifo_empty() ( SSI_SR & SSI_SR_RFE ) +#define ssi_rxfifo_noempty() ( SSI_SR & SSI_SR_RFHF ) +#define ssi_rxfifo_half_full() ( SSI_SR & SSI_SR_RFHF ) +#define ssi_txfifo_half_empty() ( SSI_SR & SSI_SR_TFHE ) +#define ssi_underrun() ( SSI_SR & SSI_SR_UNDR ) +#define ssi_overrun() ( SSI_SR & SSI_SR_OVER ) + +#define ssi_set_clk(dev_clk, ssi_clk) ( SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) + +#define ssi_receive_data() SSI_DR +#define ssi_transmit_data(v) ( SSI_DR = (v) ) + +#endif diff --git a/boot-programs/thread0.ccp b/boot-programs/keyboard.ccp similarity index 100% rename from boot-programs/thread0.ccp rename to boot-programs/keyboard.ccp diff --git a/boot-programs/lcd.ccp b/boot-programs/lcd.ccp new file mode 100644 index 0000000..4890b5e --- /dev/null +++ b/boot-programs/lcd.ccp @@ -0,0 +1,326 @@ +#pypp 0 +// Iris: micro-kernel for a capability-based operating system. +// lcd.ccp: Display driver. +// Copyright 2009 Bas Wijnen +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +#include "iris.h" + +// gpio stuff +#define D(n) (*(volatile unsigned *)(0x00 + 0x30 * n + gpio_address)) +#define DI(n) (*(volatile unsigned *)(0x04 + 0x30 * n + gpio_address)) +#define PU(n) (*(volatile unsigned *)(0x0c + 0x30 * n + gpio_address)) +#define AL(n) (*(volatile unsigned *)(0x10 + 0x30 * n + gpio_address)) +#define AU(n) (*(volatile unsigned *)(0x14 + 0x30 * n + gpio_address)) +#define IE(n) (*(volatile unsigned *)(0x20 + 0x30 * n + gpio_address)) + +// pwm stuff +#define CTR (*(volatile unsigned char *)(pwm_address + 0x00)) +#define PER (*(volatile unsigned short *)(pwm_address + 0x04)) +#define DUT (*(volatile unsigned short *)(pwm_address + 0x08)) + +#define CPM_MSCR (*(volatile unsigned *)(cpm_address + 0x20)) + +// Mapping address for I/O memory. +unsigned const gpio_address = 0x00001000 +unsigned const pwm_address = 0x00002000 +unsigned const lcd_address = 0x00003000 +unsigned const cpm_address = 0x00004000 + +//#define PWM0_BASE 0xB0050000 +//#define PWM1_BASE 0xB0051000 + +/* PWM Control Register (PWM_CTR) */ + +//#define PWM_CTR_EN (1 << 7) +//#define PWM_CTR_SD (1 << 6) +//#define PWM_CTR_PRESCALE_MASK 0x3f + +/* PWM Period Register (PWM_PER) */ + +//#define PWM_PER_PERIOD_MASK 0x3ff + +/* PWM Duty Register (PWM_DUT) */ + +//#define PWM_DUT_FDUTY (1 << 10) +//#define PWM_DUT_DUTY_MASK 0x3ff + +// Pin definitions, all in port 2. +#define PWM_ENABLE (1 << 30) +#define SPEN (1 << 0) //LCD_SPL +#define SPCK (1 << 1) //LCD_CLS +#define SPDA (1 << 2) //LCD_PS +#define LCD_RET (1 << 3) //LCD_REV //use for lcd reset + +// Lcd register definitions. +#define LCD_CFG (*(volatile unsigned *)(lcd_address + 0x00)) +#define LCD_VSYNC (*(volatile unsigned *)(lcd_address + 0x04)) +#define LCD_HSYNC (*(volatile unsigned *)(lcd_address + 0x08)) +#define LCD_VAT (*(volatile unsigned *)(lcd_address + 0x0c)) +#define LCD_DAH (*(volatile unsigned *)(lcd_address + 0x10)) +#define LCD_DAV (*(volatile unsigned *)(lcd_address + 0x14)) +#define LCD_PS (*(volatile unsigned *)(lcd_address + 0x18)) +#define LCD_CLS (*(volatile unsigned *)(lcd_address + 0x1c)) +#define LCD_SPL (*(volatile unsigned *)(lcd_address + 0x20)) +#define LCD_REV (*(volatile unsigned *)(lcd_address + 0x24)) +#define LCD_CTRL (*(volatile unsigned *)(lcd_address + 0x30)) +#define LCD_STATE (*(volatile unsigned *)(lcd_address + 0x34)) +#define LCD_IID (*(volatile unsigned *)(lcd_address + 0x38)) +#define LCD_DA0 (*(volatile unsigned *)(lcd_address + 0x40)) +#define LCD_SA0 (*(volatile unsigned *)(lcd_address + 0x44)) +#define LCD_FID0 (*(volatile unsigned *)(lcd_address + 0x48)) +#define LCD_CMD0 (*(volatile unsigned *)(lcd_address + 0x4c)) +#define LCD_DA1 (*(volatile unsigned *)(lcd_address + 0x50)) +#define LCD_SA1 (*(volatile unsigned *)(lcd_address + 0x54)) +#define LCD_FID1 (*(volatile unsigned *)(lcd_address + 0x58)) +#define LCD_CMD1 (*(volatile unsigned *)(lcd_address + 0x5c)) + + +// Bit definitions. +#define LCD_CFG_PDW_BIT 4 +#define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) + #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) +#define LCD_CFG_MODE_BIT 0 +#define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) + #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) + +#define LCD_VSYNC_VPS_BIT 16 +#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) +#define LCD_VSYNC_VPE_BIT 0 +#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) + +#define LCD_HSYNC_HPS_BIT 16 +#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) +#define LCD_HSYNC_HPE_BIT 0 +#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) + +#define LCD_VAT_HT_BIT 16 +#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) +#define LCD_VAT_VT_BIT 0 +#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) + +#define LCD_DAH_HDS_BIT 16 +#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) +#define LCD_DAH_HDE_BIT 0 +#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) + +#define LCD_DAV_VDS_BIT 16 +#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) +#define LCD_DAV_VDE_BIT 0 +#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) + +#define LCD_CTRL_BST_BIT 28 +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) +#define LCD_CTRL_RGB555 (1 << 27) +#define LCD_CTRL_OFUP (1 << 26) +#define LCD_CTRL_FRC_BIT 24 +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) +#define LCD_CTRL_PDD_BIT 16 +#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) +#define LCD_CTRL_EOFM (1 << 13) +#define LCD_CTRL_SOFM (1 << 12) +#define LCD_CTRL_OFUM (1 << 11) +#define LCD_CTRL_IFUM0 (1 << 10) +#define LCD_CTRL_IFUM1 (1 << 9) +#define LCD_CTRL_LDDM (1 << 8) +#define LCD_CTRL_QDM (1 << 7) +#define LCD_CTRL_BEDN (1 << 6) +#define LCD_CTRL_PEDN (1 << 5) +#define LCD_CTRL_DIS (1 << 4) +#define LCD_CTRL_ENA (1 << 3) +#define LCD_CTRL_BPP_BIT 0 +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) + +#define LCD_STATE_QD (1 << 7) +#define LCD_STATE_EOF (1 << 5) +#define LCD_STATE_SOF (1 << 4) +#define LCD_STATE_OFU (1 << 3) +#define LCD_STATE_IFU0 (1 << 2) +#define LCD_STATE_IFU1 (1 << 1) +#define LCD_STATE_LDD (1 << 0) + +#define LCD_CMD_SOFINT (1 << 31) +#define LCD_CMD_EOFINT (1 << 30) +#define LCD_CMD_PAL (1 << 28) +#define LCD_CMD_LEN_BIT 0 +#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) + +static void udelay (unsigned us): + for unsigned i = 0; i < us; ++i: + for unsigned k = 0; k < 100; ++k: + IE (2) &= ~SPEN + +static void mdelay (unsigned ms): + udelay (1000 * ms) + +static unsigned int get_pllout (): + unsigned plcr = CPM_PLCR1 + if (plcr & CPM_PLCR1_PLL1EN) + unsigned nf, nr, no + unsigned od[4] = {1, 2, 2, 4} + nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT + nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT + no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)] + return (JZ_EXTAL) / ((nr+2) * no) * (nf+2) + else + return JZ_EXTAL + +// level is in the range [0, 300] +static void set_backlight (unsigned level): + DUT = level + if level: + CTR = 0xbf + D (2) |= PWM_ENABLE + else: + CTR = 0x3f + D (2) &= ~PWM_ENABLE + +// Write to a register. Value must be in range [0, 0xff]. +static void write_reg (unsigned reg, unsigned value): + unsigned data = (reg << 0xa) | 0x200 | value + D (2) |= SPEN + D (2) = (D (2) & ~SPDA) | SPCK + D (2) &= ~SPEN + udelay(25) + for unsigned i = 0; i < 16; ++i: + D (2) &= ~SPCK + if data & 0x8000: + D (2) |= SPDA + else: + D (2) &= ~SPDA + udelay (25) + D (2) |= SPCK + udelay (25) + data <<= 1 + D (2) |= SPEN + udelay(200) + +static void lcd_enable (): + udelay (50) + D (2) &= ~LCD_RET + mdelay(150) + D (2) |= LCD_RET + mdelay(10) + // These values have been copied from the linux source. + // I have no idea what they do. + write_reg (0x00, 0x03) + write_reg (0x01, 0x40) + write_reg (0x02, 0x11) + write_reg (0x03, 0xcd) + write_reg (0x04, 0x32) + write_reg (0x05, 0x0e) + write_reg (0x07, 0x03) + write_reg (0x08, 0x08) + write_reg (0x09, 0x32) + write_reg (0x0A, 0x88) + write_reg (0x0B, 0xc6) + write_reg (0x0C, 0x20) + write_reg (0x0D, 0x20) + set_backlight (300) + +static void lcd_disable (): + write_reg (0x00, 0x03) + set_backlight (0) + +static void reset (): + // Use gpio pins as pwm. + AUR (2) = (AUR (2) & ~0x0fffffff) | 0x50000000 + // Use gpio pins as lcd master. + ALR (1) = (ALR (1) & ~0x0000ffff) | 0x55550000 + AUR (1) = 0x556a5555 + + // initialize things. + IE(2) &= ~(PWM_ENABLE | LCD_RET | SPEN | SPCK | SPDA) + DI(2) |= PWM_ENABLE | LCD_RET | SPEN | SPCK | SPDA + udelay (50) + D (2) &= ~LCD_RET + mdelay (150) + D (2) |= LCD_RET + mdelay (10) + lcd_enable () + + // For now, support only 16 bpp. + // Screen is 800x480 tft. + LCD_CTRL = LCD_CTRL_BPP_16 | LCD_CTRL_BST_16 + LCD_VSYNC = 20 + LCD_HSYNC = 80 + LCD_DAV = (20 << 16) | 500 + LCD_DAH = (80 << 16) | 880 + LCD_VAT = (880 << 16) | 500 + LCD_CFG = MODE_TFT_GEN | PCLK_N | VSYNC_N + + // Stop lcd. + CPM_MSCR |= 1 << 7 + + unsigned pclk = 60 * (800 * 3 + 80) * 500 + unsigned pllout = get_pllout () + CPM_CFCR2 = pllout / pclk - 1 + unsigned v = pllout / (pclk * 4) - 1 + while v < 0xf && pllout / (v + 1) > 150000000: + ++v + CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_LFR_MASK) | (v << CPM_CFCR_LFR_BIT) | CPM_CFCR_UPE + + // Start lcd. + CPM_MSCR &= ~(1 << 7) + mdelay (1) + +static void map_io (unsigned physical, unsigned address): + Capability page = memory_create_page (__my_memory) + alloc_physical (page, physical, 0) + memory_map (__my_memory, page, address, 1) + //drop (page) + +int main (): + map_io (0x10010000, gpio_address) + map_io (0x10050000, pwm_address) + map_io (0x13050000, lcd_address) + map_io (0x10000000, cpm_address) + + reset () + + while true: + Message msg + if !wait (&msg): + continue + switch msg.protected_data: + case LCD_BACKLIGHT: + set_backlight (c.data[0] > 300 ? 300 : c.data[0]) + break + case LCD_RESET: + reset () + break diff --git a/boot-programs/thread1.ccp b/boot-programs/thread1.ccp deleted file mode 100644 index a3e3096..0000000 --- a/boot-programs/thread1.ccp +++ /dev/null @@ -1,23 +0,0 @@ -#pypp 0 -// Iris: micro-kernel for a capability-based operating system. -// thread1.ccp: Testing userspace thread. -// Copyright 2009 Bas Wijnen -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -#include "iris.h" - -int main (): - while true: - schedule () diff --git a/invoke.ccp b/invoke.ccp index d3c5c19..e64a255 100644 --- a/invoke.ccp +++ b/invoke.ccp @@ -30,7 +30,6 @@ Capability *Memory::find_capability (unsigned code, bool *copy): if p->data.frame == (unsigned)page: return &page[num] else: - code &= ~3 // Normal capability for Capability *c = capabilities; c; c = c->next: if c == (Capability *)code: @@ -47,37 +46,36 @@ bool Receiver::try_deliver (): break if !m: return false - Capability::Context c + Capability *c[4] for unsigned i = 0; i < 4; ++i: - c.data[i] = m->data[i] if !m->capabilities[i]: - c.cap[i] = NULL + c[i] = NULL else: - c.cap[i] = owner->address_space->clone_capability (m->capabilities[i], true) - if !c.cap[i]: + c[i] = owner->address_space->clone_capability (m->capabilities[i], true) + if !c[i]: for unsigned j = 0; j < i; ++j: - owner->address_space->free_capability (c.cap[i]) + owner->address_space->free_capability (c[i]) return false - Thread_arch_receive (owner, &c) + Thread_arch_receive (owner, m->data, c) owner->unwait () return true -bool Receiver::send_message (unsigned protected_data, Capability::Context *c): +bool Receiver::send_message (unsigned protected_data, unsigned data[4], Capability *cap[4], bool copy[4]): bool tried_direct = false if owner && owner->is_waiting () && (protected_data == reply_protected_data || !protected_only): - Capability::Context n + Capability *c[4] for unsigned i = 0; i < 4; ++i: - if !c->cap[i]: - n.cap[i] = NULL + if !cap[i]: + c[i] = NULL else: - n.cap[i] = owner->address_space->clone_capability (c->cap[i], c->copy[i]) - if !n.cap[i]: + c[i] = owner->address_space->clone_capability (cap[i], copy[i]) + if !c[i]: for unsigned j = 0; j < i; ++j: - owner->address_space->free_capability (n.cap[i]) + owner->address_space->free_capability (c[i]) tried_direct = true break if !tried_direct: - Thread_arch_receive (owner, &n) + Thread_arch_receive (owner, data, c) owner->unwait () return true // The owner was not waiting, or it was not possible to deliver the message. Put it in the queue. @@ -85,11 +83,11 @@ bool Receiver::send_message (unsigned protected_data, Capability::Context *c): if !msg: return false for unsigned i = 0; i < 4; ++i: - msg->data[i] = c->data[i] - if !c->cap[i]: + msg->data[i] = data[i] + if !cap[i]: msg->capabilities[i] = NULL else: - msg->capabilities[i] = address_space->clone_capability (c->cap[i], c->copy[i]) + msg->capabilities[i] = address_space->clone_capability (cap[i], copy[i]) if !msg->capabilities[i]: for unsigned j = 0; j < i; ++j: address_space->free_capability (msg->capabilities[j]) @@ -109,6 +107,8 @@ static void fill_cap (Capability *r, unsigned target, unsigned protected_data): ref = &((Receiver *)target)->capabilities else: ref = &((Object_base *)protected_data)->refs + // alloc_capability needs a Memory, but it isn't used if return storage is given. + ref = &((Object_base *)protected_data)->refs // alloc_capability needs a Memory, but it isn't used if return storage is given. top_memory.alloc_capability ((Receiver *)target, NULL, ref, protected_data, r) @@ -628,91 +628,52 @@ static void page_invoke (unsigned target, unsigned protected_data, Capability::C if !p: new_flags &= ~PAGE_FLAG_FRAME // If we can get the new frame, get it. - if new_flags & PAGE_FLAG_FRAME: - share_data->frame = raw_zalloc () - - // If the frame is lost, the page is no longer shared. - if old & ~new_flags & PAGE_FLAG_FRAME: - new_flags &= ~PAGE_FLAG_SHARED - if page: - if share_data->share_prev: - ((Page *)share_data->share_prev)->data.share_next = share_data->share_next - if share_data->share_next: - ((Page *)share_data->share_next)->data.share_prev = share_data->share_prev - else: - if share_data->share_prev: - ((Cappage *)share_data->share_prev)->data.share_next = share_data->share_next - if share_data->share_next: - ((Cappage *)share_data->share_next)->data.share_prev = share_data->share_prev - share_data->share_prev = NULL - share_data->share_next = NULL - - // Set the shared flag. - if share_data->share_prev || share_data->share_next: - new_flags |= PAGE_FLAG_SHARED - // Don't allow making shared pages writable. - if ~old & PAGE_FLAG_WRITABLE: - new_flags &= ~PAGE_FLAG_WRITABLE - else: - new_flags &= ~PAGE_FLAG_SHARED - - // Actually set the new flags. - share_data->flags = new_flags - - // Update mappings if there is a change in writability, or in frame. - if page && ((share_data->flags ^ old) & PAGE_FLAG_WRITABLE || (share_data->flags ^ old) & PAGE_FLAG_FRAME): - Page_arch_update_mapping (page) - reply_num (share_data->flags) - break - case CAP_CAPPAGE_SET: - if !cappage || c->data[1] >= CAPPAGE_SIZE || !(target & CAP_PAGE_WRITE): - return - Capability *cap = &((Capability *)cappage->data.frame)[c->data[1]] - if cap: - cap->invalidate () - // clone_capability needs a Memory, but doesn't use it when storage is provided. - top_memory.clone_capability (c->cap[0], c->copy[0], cap) + Capability *c = &((Capability *)cappage->data.frame)[data[1]] + c->invalidate () + // clone_capability needs a Memory, but doesn't use it when storage is provided. + top_memory.clone_capability (cap, copy, c) break default: break -static void capability_invoke (unsigned target, unsigned protected_data, Capability::Context *c): +static void capability_invoke (unsigned target, unsigned protected_data, Capability *cap, unsigned request, unsigned data): Capability *capability = (Capability *)protected_data - switch c->data[0]: + switch request: case CAP_CAPABILITY_GET: reply_cap (capability, true) break default: break -static bool kernel_invoke (unsigned target, unsigned protected_data, Capability::Context *c, Capability *self): +static bool kernel_invoke (unsigned target, unsigned protected_data, unsigned d[4], Capability *c[4], bool copy[4], Capability *self): // Kernel calling convention: // data[0] is the request. // cap[0] is the reply capability // other parameters' meanings depend on the operation. + if !((1 << d[0]) & target & ~REQUEST_MASK): + // You are not allowed to perform this operation. + return true if (target & (CAPTYPE_MASK | (1 << CAP_RECEIVER_CALL))) == (CAPTYPE_RECEIVER | (1 << CAP_RECEIVER_CALL)): // This is a call capability. reply_receiver = (Receiver *)protected_data reply_receiver->protected_only = !(target & (1 << CAP_RECEIVER_CALL_ASYNC)) Capability r - Capability *c0 = c->cap[0] - if (unsigned)c0->target & ~KERNEL_MASK: - // The call is not to a kernel capability. + Capability *c0 = c[0] + if ~(unsigned)c0->target & ~KERNEL_MASK: fill_cap (&r, protected_data, reply_receiver->reply_protected_data) - c->cap[0] = &r - c->copy[0] = true - bool ret = c0->target->send_message (c0->protected_data, c) + c[0] = &r + copy[0] = true + bool ret = kernel_invoke ((unsigned)c0->target, c0->protected_data, d, c, copy, c0) r.invalidate () return ret else: // Kernel call: don't create actual capablities. reply = NULL - kernel_invoke ((unsigned)c0->target, c0->protected_data, c, c0) - return true + return kernel_invoke ((unsigned)c0->target, c0->protected_data, d, c, copy, c0) if (target & (CAPTYPE_MASK | (1 << CAP_RECEIVER_REPLY))) == (CAPTYPE_RECEIVER | (1 << CAP_RECEIVER_REPLY)): // This is a reply capability. Receiver *r = (Receiver *)protected_data - r->send_message (r->reply_protected_data, c) + r->send_message (r->reply_protected_data, d, c, copy) while self->parent: self = self->parent while self->sibling_prev: @@ -721,42 +682,36 @@ static bool kernel_invoke (unsigned target, unsigned protected_data, Capability: self->sibling_next->invalidate () self->invalidate () return true - // It's a normal kernel capability; check permission. - if !((1 << c->data[0]) & target & REQUEST_MASK): - // You are not allowed to perform this operation. - dbg_send (c->data[0], 5) - schedule () - return true - if c->data[0] == CAP_DEGRADE: - reply_cap (target & (CAPTYPE_MASK | (c->data[1] & REQUEST_MASK)), protected_data) + reply = c[0] + if d[0] == CAP_DEGRADE: + reply_cap (target & d[1], protected_data) return true switch target & CAPTYPE_MASK: case CAPTYPE_RECEIVER: - receiver_invoke (target, protected_data, c) + receiver_invoke (target, protected_data, c[1], d) break case CAPTYPE_MEMORY: - memory_invoke (target, protected_data, c) + memory_invoke (target, protected_data, c[1], d[0], d[1]) break case CAPTYPE_THREAD: - thread_invoke (target, protected_data, c) + thread_invoke (target, protected_data, c[1], d) break case CAPTYPE_PAGE: - page_invoke (target, protected_data, c) + page_invoke (target, protected_data, c[1], copy[1], d) break case CAPTYPE_CAPABILITY: - capability_invoke (target, protected_data, c) + capability_invoke (target, protected_data, c[1], d[0], d[1]) break case CAPTYPE_CAPPAGE: + page_invoke (target, protected_data, c[1], copy[1], d) break default: panic (0x99337744, "invalid capability type invoked") return true -bool Capability::invoke (Context *c): +bool Capability::invoke (unsigned data[4], Capability *cap[4], bool copy[4]): if (unsigned)target & ~KERNEL_MASK: // This is not a kernel capability: send a message to the receiver. - return target->send_message (protected_data, c) + return target->send_message (protected_data, data, cap, copy) // This is a kernel capability. Use a function to allow optimized call capabilities. - reply = c->cap[0] - reply_receiver = NULL - return kernel_invoke ((unsigned)target, protected_data, c, this) + return kernel_invoke ((unsigned)target, protected_data, data, cap, copy, this) diff --git a/iris.h b/iris.h index 81c24a2..d18ccc5 100644 --- a/iris.h +++ b/iris.h @@ -138,6 +138,7 @@ typedef struct Message { unsigned data[4]; Capability cap[4]; + unsigned protected_data; /* only used for receiving. */ } Message; static int invoke (Capability target, Message *msg) @@ -161,22 +162,26 @@ static int invoke (Capability target, Message *msg) return ret; } -static void wait (Message *msg) +static int wait (Message *msg) { + int ret; __asm__ volatile ("li $v0, 2\n" "\tsyscall\n" - "\tlw $v1, %0\n" - "\tsw $t0, 0($v1)\n" - "\tsw $t1, 4($v1)\n" - "\tsw $t2, 8($v1)\n" - "\tsw $t3, 12($v1)\n" - "\tsw $a0, 16($v1)\n" - "\tsw $a1, 20($v1)\n" - "\tsw $a2, 24($v1)\n" - "\tsw $a3, 28($v1)" - : + "\tsw $v0, %0\n" + "\tlw $v0, %1\n" + "\tsw $t0, 0($v0)\n" + "\tsw $t1, 4($v0)\n" + "\tsw $t2, 8($v0)\n" + "\tsw $t3, 12($v0)\n" + "\tsw $a0, 16($v0)\n" + "\tsw $a1, 20($v0)\n" + "\tsw $a2, 24($v0)\n" + "\tsw $a3, 28($v0)\n" + "\tsw $v1, 32($v0)" + : "=m"(ret) : "m"(msg) : "memory", "v0", "v1", "t0", "t1", "t2", "t3", "a0", "a1", "a2", "a3"); + return ret } static int call (Capability target, Message *msg) @@ -194,16 +199,18 @@ static int call (Capability target, Message *msg) "\tlw $a2, 24($v1)\n" "\tlw $a3, 28($v1)\n" "\tsyscall\n" - "\tmove %0, $v0\n" - "\tsw $t0, 0($v1)\n" - "\tsw $t1, 4($v1)\n" - "\tsw $t2, 8($v1)\n" - "\tsw $t3, 12($v1)\n" - "\tsw $a0, 16($v1)\n" - "\tsw $a1, 20($v1)\n" - "\tsw $a2, 24($v1)\n" - "\tsw $a3, 28($v1)" - : "=r"(ret) + "\tsw $v0, %0\n" + "\tlw $v0, %2\n" + "\tsw $t0, 0($v0)\n" + "\tsw $t1, 4($v0)\n" + "\tsw $t2, 8($v0)\n" + "\tsw $t3, 12($v0)\n" + "\tsw $a0, 16($v0)\n" + "\tsw $a1, 20($v0)\n" + "\tsw $a2, 24($v0)\n" + "\tsw $a3, 28($v0)\n" + "\tsw $v1, 32($v0)" + : "=m"(ret) : "m"(t), "m"(msg) : "memory", "v0", "v1", "t0", "t1", "t2", "t3", "a0", "a1", "a2", "a3"); } diff --git a/mips/Makefile.arch b/mips/Makefile.arch index 069b633..e156743 100644 --- a/mips/Makefile.arch +++ b/mips/Makefile.arch @@ -28,7 +28,7 @@ arch_kernel_sources = mips/interrupts.cc mips/test.cc mips/arch.cc boot_sources = mips/init.cc BUILT_SOURCES = $(kernel_sources) $(boot_sources) arch_headers = mips/arch.hh -boot_threads = thread0 thread1 +boot_threads = keyboard lcd uimage: diff --git a/mips/arch.ccp b/mips/arch.ccp index 2161e7e..1d62673 100644 --- a/mips/arch.ccp +++ b/mips/arch.ccp @@ -54,6 +54,7 @@ void Thread_arch_receive (Thread *thread, Capability::Context *c): thread->arch.t1 = c->data[1] thread->arch.t2 = c->data[2] thread->arch.t3 = c->data[3] + thread->arch.v1 = c->protected_data thread->arch.v0 = 1 void Thread_arch_receive_fail (Thread *thread):