enable tp4+5 uart; don't enable uart receive on keyboard pin

mips/nanonote/board.ccp

@@ -62,8 +62,6 @@ void board_init ():
 	gpio_disable_pull (3, (1 << 0) | (1 << 2))
 	// Disable power to sd/mmc by default.
 	gpio_set (3, 1 << 2)
-	// Set up keyboard: this breaks uart receive.
-	gpio_as_gpio (3, 0x05fc0000)
 	// Set up timed interrupts.
 	tcu_start_timer_clock (0)
 	tcu_stop_counter (0)
@@ -76,7 +74,7 @@ void board_init ():
 	tcu_unmask_full_match_irq (0)
 	tcu_start_counter (0)
 	#ifndef NDEBUG
-	setup_uart ()
+	setup_uart (true)
 	kdebug ("\n\nSerial port initialized\n")
 	#endif
 

mips/nanonote/jz4740.hhp

@@ -2188,11 +2188,11 @@ static void gpio_as_nand ():
 	GPIO_PXFUNS (1) = 0x00400000
 	GPIO_PXSELC (1) = 0x00400000
 
-// UART0_TxD, UART_RxD0
-static void gpio_as_uart0 ():
-	GPIO_PXFUNS (3) = 0x06000000
-	GPIO_PXSELS (3) = 0x06000000
-	GPIO_PXPES (3) = 0x06000000
+// UART0_TxD, UART0_RxD
+static void gpio_as_uart0 (bool send_only = false):
+	GPIO_PXFUNS (3) = send_only ? 0x02000000 : 0x06000000
+	GPIO_PXSELS (3) = send_only ? 0x02000000 : 0x06000000
+	GPIO_PXPES (3) = send_only ? 0x02000000 : 0x06000000
 
 // UART0_CTS, UART0_RTS
 static void gpio_as_ctsrts ():
@@ -2201,6 +2201,14 @@ static void gpio_as_ctsrts ():
 	GPIO_PXTRGC (3) = 0xc0000000
 	GPIO_PXPES (3) = 0xc0000000
 
+// JTAG on pad 147+148 (Jz4720)
+static void enable_jtag_debug ():
+	GPIO_PXSELC (3) = 0x80000000
+
+// UART0 on pad 147+148 (Jz4720)
+static void enable_uart0_debug ():
+	GPIO_PXSELS (3) = 0x80000000
+
 // UART1_TxD, UART1_RxD1
 static void gpio_as_uart1():
 	GPIO_PXFUNS (3) = 0xc0000000
@@ -3601,7 +3609,7 @@ static void setup_sdram ():
 
 	cpu_clk = 252000000
 	gpio_as_sdram_16bit ()
-	unsigned SDRAM_BW16 = 0
+	unsigned SDRAM_BW16 = 1
 	unsigned SDRAM_BANK4 = 1
 	unsigned SDRAM_ROW = 12
 	unsigned SDRAM_COL = 8
@@ -3609,10 +3617,11 @@ static void setup_sdram ():
 	mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()]
 	EMC_BCR = 0
 	EMC_RTCSR = 0
+	unsigned SDRAM_BW160 = 0
 	unsigned SDRAM_ROW0 = 11
 	unsigned SDRAM_COL0 = 8
 	unsigned SDRAM_BANK40 = 0
-	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
+	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW160<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
 	// Basic DMCR value
 	dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
 	// SDRAM timimg
@@ -3703,11 +3712,12 @@ static void setup_sdram ():
 	dbg_log ("\n")
 	#endif
 
-static void setup_uart ():
-	#ifndef NDEBUG
+static void setup_uart (bool send_only = false):
 	// Set up uart.
+	#ifndef NDEBUG
 	cpm_start_uart0 ()
-	gpio_as_uart0 ()
+	enable_uart0_debug ()
+	gpio_as_uart0 (send_only)
 	UART0_IER = 0
 	UART0_FCR = 0
 	UART0_MCR = 0

mips/nanonote/nand-boot.ccp

@@ -138,7 +138,7 @@ extern "C":
 		gpio_as_sdram_16bit ()
 		gpio_as_nand ()
 		setup_sdram ()
-		setup_uart ()
+		setup_uart (true)
 		reset ()
 		// Load contents of nand flash (from 0x4000) into 0xa0600000;
 		unsigned a = 0x4000

mips/nanonote/stage1.ccp

@@ -58,7 +58,7 @@ extern "C":
 	char stack[0x40]
 
 void start_cpp (int skip_memsetup):
-	setup_uart ()
+	setup_uart (true)
 	kdebug ('.')
 	if !skip_memsetup:
 		setup_sdram ()