working keyboard

mips/Makefile.arch

@@ -17,7 +17,7 @@
 
 load = 0x80000000
 
-ARCH_CXXFLAGS = -DNUM_THREADS=2
+ARCH_CXXFLAGS = -DNUM_THREADS=1
 ARCH_CPPFLAGS = -Imips -Wa,-mips32
 CROSS = mipsel-linux-gnu-
 OBJDUMP = $(CROSS)objdump
@@ -40,9 +40,6 @@ $(boot_threads): TARGET_FLAGS = -I.
 uimage: kernel.raw.gz Makefile mips/Makefile.arch
 	mkimage -A MIPS -O Linux -C gzip -a $(load) -e 0x$(shell /bin/sh -c '$(OBJDUMP) -t kernel | grep __start$$ | cut -b-8') -n "Shevek's kernel" -d $< $@ | sed -e 's/:/;/g'
 
-elf.h: /usr/include/elf.h
-	ln -s $< $@
-
 %.o:%.S Makefile mips/Makefile.arch mips/arch.hh
 	$(CC) $(CPPFLAGS) $(TARGET_FLAGS) -DKERNEL_STACK_SIZE=0x2000 -c $< -o $@
 
@@ -56,4 +53,4 @@ kernel: mips/entry.o $(subst .cc,.o,$(kernel_sources)) mips/boot.o $(subst .cc,.
 %.gz: %
 	gzip < $< > $@
 
-ARCH_CLEAN_FILES = uimage kernel kernel.raw kernel.raw.gz elf.h $(boot_threads) mips/*.o
+ARCH_CLEAN_FILES = uimage kernel kernel.raw kernel.raw.gz $(boot_threads) mips/*.o

mips/arch.ccp

@@ -45,15 +45,15 @@ void Thread_arch_init (Thread *thread):
 	thread->arch.k0 = 0
 	thread->arch.k1 = 0
 
-void Thread_arch_receive (Thread *thread, unsigned d[4], Capability *c[4]):
-	thread->arch.a0 = (unsigned)c[0]
-	thread->arch.a1 = (unsigned)c[1]
-	thread->arch.a2 = (unsigned)c[2]
-	thread->arch.a3 = (unsigned)c[3]
-	thread->arch.t0 = d[0]
-	thread->arch.t1 = d[1]
-	thread->arch.t2 = d[2]
-	thread->arch.t3 = d[3]
+void Thread_arch_receive (Thread *thread, Capability::Context *c):
+	thread->arch.a0 = (unsigned)c->cap[0]
+	thread->arch.a1 = (unsigned)c->cap[1]
+	thread->arch.a2 = (unsigned)c->cap[2]
+	thread->arch.a3 = (unsigned)c->cap[3]
+	thread->arch.t0 = c->data[0]
+	thread->arch.t1 = c->data[1]
+	thread->arch.t2 = c->data[2]
+	thread->arch.t3 = c->data[3]
 	thread->arch.v0 = 1
 
 void Thread_arch_receive_fail (Thread *thread):
@@ -222,10 +222,12 @@ static unsigned make_entry_lo (Page *page, bool write):
 	if !page->data.frame:
 		return 0
 	unsigned flags
-	if write:
-		flags = 0x18 | 0x4 | 0x2
-	else
+	if page->data.flags & PAGE_FLAG_UNCACHED:
+		flags = 0x10 | 0x2
+	else:
 		flags = 0x18 | 0x2
+	if write:
+		flags |= 0x4
 	return ((page->data.frame & ~0x80000000) >> 6) | flags
 
 bool Memory_arch_map (Memory *mem, Page *page, unsigned address, bool write):
@@ -320,30 +322,36 @@ void Page_arch_update_mapping (Page *page):
 		tlb_reset (p->mapping & ~1, as->arch.asid, t)
 
 void arch_invoke ():
-	Capability *target, *c[4]
-	bool wait, copy[4]
+	Capability *target
+	bool wait
 	Thread *caller = current
 	target = caller->address_space->find_capability (current->arch.v0, &wait)
 	if !target:
 		// TODO: there must be no action here.  This is just because the rest doesn't work yet.
-		dbg_led (caller->arch.a0, caller->arch.a1, caller->arch.a2)
-		dbg_sleep (1000)
+		dbg_send (3, 2)
 		schedule ()
 		// Calling an invalid capability always fails.
 		caller->arch.v0 = 0
 	else:
 		if wait:
 			caller->wait ()
-		c[0] = caller->address_space->find_capability (caller->arch.a0, &copy[0])
-		c[1] = caller->address_space->find_capability (caller->arch.a1, &copy[1])
-		c[2] = caller->address_space->find_capability (caller->arch.a2, &copy[2])
-		c[3] = caller->address_space->find_capability (caller->arch.a3, &copy[3])
-		unsigned d[4]
-		d[0] = caller->arch.t0
-		d[1] = caller->arch.t1
-		d[2] = caller->arch.t2
-		d[3] = caller->arch.t3
-		caller->arch.v0 = target->invoke (d, c, copy) ? 1 : 0
+		Capability::Context c
+		c.cap[0] = caller->address_space->find_capability (caller->arch.a0, &c.copy[0])
+		c.cap[1] = caller->address_space->find_capability (caller->arch.a1, &c.copy[1])
+		c.cap[2] = caller->address_space->find_capability (caller->arch.a2, &c.copy[2])
+		c.cap[3] = caller->address_space->find_capability (caller->arch.a3, &c.copy[3])
+		c.data[0] = caller->arch.t0
+		c.data[1] = caller->arch.t1
+		c.data[2] = caller->arch.t2
+		c.data[3] = caller->arch.t3
+		caller->arch.v0 = target->invoke (&c) ? 1 : 0
+	if !current:
+		if caller != &idle && (caller->flags & (THREAD_FLAG_RUNNING | THREAD_FLAG_WAITING)) == THREAD_FLAG_RUNNING:
+			current = caller
+		else:
+			schedule ()
+			if !current:
+				current = &idle
 	if caller != current:
 		if (Memory *)asids[current->address_space->arch.asid] != current->address_space:
 			if asids[0]:

mips/arch.hhp

@@ -61,10 +61,6 @@
 #define CP0_DESAVE 31
 #endif
 
-#define PAGE_BITS (12)
-#define PAGE_SIZE (1 << PAGE_BITS)
-#define PAGE_MASK (~(PAGE_SIZE - 1))
-
 // register save positions in Thread
 #define SAVE_PC (5 * 4)
 #define SAVE_SP (SAVE_PC + 4)

mips/entry.S

@@ -80,7 +80,7 @@ addr_100:
 addr_180:
 	// General exception
 	// Allow new exceptions to update EPC and friends.
-	//mtc0 $zero, $CP0_STATUS
+	mtc0 $zero, $CP0_STATUS
 	sw $ra, -0xd88($zero)
 	bal save_regs
 	nop

mips/init.ccp

@@ -178,10 +178,12 @@ static void init_threads ():
 		if !stackpage || !mem->map (stackpage, 0x7ffff000, true):
 			panic (0x13151719, "unable to map initial stack page")
 		Receiver *recv = mem->alloc_receiver ()
+		recv->owner = thread
+		thread->receivers = recv
 		thread->arch.a0 = mkcap (mem, CAPTYPE_RECEIVER | CAP_RECEIVER_ALL_RIGHTS, recv)
 		thread->arch.a1 = mkcap (mem, CAPTYPE_THREAD | CAP_THREAD_ALL_PRIV_RIGHTS, thread)
 		thread->arch.a2 = mkcap (mem, CAPTYPE_MEMORY | CAP_MEMORY_ALL_RIGHTS, mem)
-		thread->arch.a3 = mkcap (mem, CAPTYPE_RECEIVER | CAP_RECEIVER_CALL, recv)
+		thread->arch.a3 = mkcap (mem, CAPTYPE_RECEIVER | (1 << CAP_RECEIVER_CALL), recv)
 		mem->pfree ((unsigned)pages)
 		thread->flags = THREAD_FLAG_RUNNING | THREAD_FLAG_PRIV
 		thread->schedule_next = NULL

mips/interrupts.ccp

@@ -30,6 +30,11 @@ Thread *tlb_refill ():
 	cp0_get (CP0_ENTRY_HI, EntryHi)
 	unsigned *t = directory[EntryHi >> 21]
 	if !t:
+		unsigned a
+		cp0_get (CP0_EPC, a)
+		dbg_send (a)
+		cp0_get (CP0_BAD_V_ADDR, a)
+		dbg_send (a)
 		panic (0x99992222, "No page table")
 	// - 2 instead of - 1 means reset bit 0
 	unsigned idx = (EntryHi >> 12) & ((1 << 9) - 2)
@@ -50,17 +55,18 @@ Thread *interrupt ():
 			status &= ~(1 << (i + 8))
 			// Send message to interrupt handler.
 			if arch_interrupt_receiver[i]:
-				unsigned data[4] = {0, 0, 0, 0}
-				Capability *cap[4] = {NULL, NULL, NULL, NULL}
-				bool copy[4] = {false, false, false, false}
-				arch_interrupt_receiver[i]->send_message (i, data, cap, copy)
+				Capability::Context c
+				for unsigned j = 0; j < 4; ++j:
+					c.data[j] = 0
+					c.cap[j] = NULL
+					c.copy[j] = false
+				arch_interrupt_receiver[i]->send_message (i, &c)
 	return current
 
 /// A general exception has occurred.
 Thread *exception ():
 	unsigned cause
 	cp0_get (CP0_CAUSE, cause)
-	//dbg_send (cause >> 2, 5)
 	switch (cause >> 2) & 0x1f:
 		case 0:
 			// Interrupt.  This shouldn't happen, since CAUSE[IV] == 1.
@@ -70,6 +76,9 @@ Thread *exception ():
 			panic (0x21223344, "TLB modification.")
 		case 2:
 			// TLB load or instruction fetch.
+			unsigned a
+			cp0_get (CP0_EPC, a)
+			dbg_send (a)
 			panic (0x31223344, "TLB load or instruction fetch.")
 		case 3:
 			// TLB store.
@@ -79,6 +88,9 @@ Thread *exception ():
 			panic (0x51223344, "Address error load or instruction fetch.")
 		case 5:
 			// Address error store.
+			unsigned a
+			cp0_get (CP0_EPC, a)
+			dbg_send (a, 16)
 			panic (0x61223344, "Address error store.")
 		case 6:
 			// Bus error instruction fetch.
@@ -88,6 +100,7 @@ Thread *exception ():
 			panic (0x81223344, "Bus error load or store.")
 		case 8:
 			// Syscall.
+			current->pc += 4
 			arch_invoke ()
 			break
 		case 9: