lots of stuff

2025-04-21 12:27:27 +03:00 · 2009-10-31 09:32:23 +01:00
parent afb496f20b
commit a383b3ffd3
28 changed files with 441 additions and 230 deletions
--- a/mips/Makefile.arch
+++ b/mips/Makefile.arch
@@ -1 +1 @@
-board/Makefile.arch
+nanonote/Makefile.arch
--- a/mips/arch.ccp
+++ b/mips/arch.ccp
@@ -185,6 +185,7 @@ static unsigned make_entry_lo (kPage *page, bool readonly):
 	if page->flags & Kernel::Page::UNCACHED:
 		flags = 0x10 | 0x2
 	else:
+		// 18 is write-back cache; 00 is write-through cache.
 		flags = 0x18 | 0x2
 	if !readonly:
 		flags |= 0x4
@@ -289,15 +290,3 @@ void arch_register_interrupt (unsigned num, kReceiver *r):
 		intc_unmask_irq (num)
 	else:
 		intc_mask_irq (num)
-
-void arch_reboot ():
-	// Wait for serial port to be done.
-	while !(UART0_LSR & UARTLSR_TEMT):
-	// Reboot.
-	wdt_select_extalclk ()
-	wdt_select_clk_div1 ()
-	wdt_set_data (1)
-	wdt_set_count (0)
-	wdt_start ()
-	// Wait for wdt to trigger reboot.
-	while true:
--- a/mips/arch.hhp
+++ b/mips/arch.hhp
@@ -69,7 +69,7 @@

 #endif

-#ifdef __KERNEL
+#ifdef __KERNEL__
 // register save positions in kThread
 #define SAVE_PC (6 * 4)
 #define SAVE_SP (SAVE_PC + 4)
@@ -147,6 +147,6 @@ extern unsigned **directory

 #endif // not defined ASM

-#endif // defined __KERNEL
+#endif // defined __KERNEL__

 #endif
--- a/mips/entry.S
+++ b/mips/entry.S
@@ -25,7 +25,7 @@

 #define ARCH
 #define ASM
-#define __KERNEL
+#define __KERNEL__
 #include "arch.hh"

 addr_000:
@@ -118,7 +118,7 @@ start_idle:			// 280
 // TODO: save only fragile registers now, the rest on task switch.
 kernel_exit:
 #ifndef NDEBUG
-	// Interrupts were enabled in the kernel; set them to usermode setting again.
+	// Exceptions were enabled in the kernel; set them to usermode setting again.
 	mfc0 $k0, $CP0_STATUS
 	ori $k0, $k0, 0xff13
 	mtc0 $k0, $CP0_STATUS
@@ -217,7 +217,7 @@ save_regs:
 #ifndef NDEBUG
 	// Allow kernel bugs to set EPC and friends.
 	mfc0 $k0, $CP0_STATUS
-	li $k1, 0x1000ff00
+	li $k1, 0x10000000
 	and $k0, $k0, $k1
 	mtc0 $k0, $CP0_STATUS
 #endif
--- a/mips/nanonote/Makefile.arch
+++ b/mips/nanonote/Makefile.arch
@@ -17,7 +17,7 @@

 load = 0x80000000

-ARCH_CXXFLAGS = -DNUM_THREADS=5
+ARCH_CXXFLAGS = -DNUM_THREADS=6
 ARCH_CPPFLAGS = -I. -Imips -Imips/nanonote -Wa,-mips32 -DNANONOTE -DUSE_SERIAL
 CROSS = mipsel-linux-gnu-
 OBJDUMP = $(CROSS)objdump
@@ -28,7 +28,7 @@ LDFLAGS = --omagic -Ttext $(load)
 arch_iris_sources = mips/interrupts.cc mips/arch.cc
 boot_sources = mips/init.cc mips/nanonote/board.cc
 arch_headers = mips/arch.hh mips/nanonote/jz4740.hh mips/nanonote/board.hh
-boot_threads = init udc nanonote-gpio buzzer metronome
+boot_threads = init udc nanonote-gpio buzzer metronome lcd

 test: iris.raw nanonote-boot
 	./nanonote-boot iris.raw 0xa$(shell /bin/sh -c '$(OBJDUMP) -t iris.elf | grep __start$$ | cut -b2-8')
@@ -46,10 +46,10 @@ nanonote-boot: mips/nanonote/nanonote-boot.cc mips/nanonote/sdram-setup.raw
 mips/nanonote/sdram-setup.elf: mips/nanonote/sdram-setup.ld
 mips/nanonote/sdram-setup.elf: LDFLAGS = --omagic -T mips/nanonote/sdram-setup.ld
 mips/boot.o: TARGET_FLAGS = -DMEMORY_SIZE="32 << 20"
-mips/entry.o: $(boot_threads)
+mips/entry.o: $(addsuffix .elf,$(boot_threads))
 mips/init.o: TARGET_FLAGS = -I/usr/include
-$(boot_threads): TARGET_FLAGS = -I.
-$(boot_threads): LDFLAGS = -EL
+$(addsuffix .elf,$(boot_threads)): TARGET_FLAGS = -I.
+$(addsuffix .elf,$(boot_threads)): LDFLAGS = -EL
 $(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): devices.hh keys.hh
 lcd: boot-programs/charset.data

@@ -63,4 +63,4 @@ boot-programs/charset.data: boot-programs/charset
 iris.elf: mips/entry.o $(subst .cc,.o,$(iris_sources)) mips/nanonote/threadlist.o mips/boot.o $(subst .cc,.o,$(boot_sources))
 	$(LD) $(LDFLAGS) $^ -o $@

-ARCH_CLEAN_FILES = $(boot_sources) $(boot_threads) $(arch_headers) devices.hh keys.hh mips/*.o mips/nanonote/*.o boot-programs/charset.data iris.elf iris.raw mips/nanonote/sdram-setup.elf mips/nanonote/sdram-setup.raw
+ARCH_CLEAN_FILES = $(boot_sources) $(addsuffix .elf,$(boot_threads)) $(arch_headers) devices.hh keys.hh mips/*.o mips/nanonote/*.o boot-programs/charset.data iris.elf iris.raw mips/nanonote/sdram-setup.elf mips/nanonote/sdram-setup.raw
--- a/mips/nanonote/board.ccp
+++ b/mips/nanonote/board.ccp
@@ -27,9 +27,15 @@ void board_init ():
 	gpio_as_sdram_16bit ()
 	gpio_as_nand ()
 	gpio_as_aic ()
-	gpio_as_lcd_16bit ()
 	gpio_as_msc ()
+	gpio_as_lcd_16bit ()
+	// Set up memory.
 	setup_sdram ()
+	// Use some gpio pins for lcd.
+	gpio_as_gpio (2, (1 << 21) | (1 << 22) | (1 << 23))
+	gpio_as_gpio (3, 1 << 27)
+	gpio_as_output (2, (1 << 21) | (1 << 22) | (1 << 23))
+	gpio_as_output (3, 1 << 27)
 	// Set up keyboard: this breaks uart receive.
 	gpio_as_gpio (3, 0x05fc0000)
 	tcu_stop_counter (0)
@@ -56,3 +62,15 @@ void board_init ():
 	UART0_FCR = UARTFCR_UUE | UARTFCR_FE | UARTFCR_RFLS | UARTFCR_TFLS
 	dbg_code.l = 1
 	dbg_log ("Serial port initialized\n")
+
+void arch_reboot ():
+	// Wait for serial port to be done.
+	while !(UART0_LSR & UARTLSR_TEMT):
+	// Reboot.
+	wdt_select_extalclk ()
+	wdt_select_clk_div1 ()
+	wdt_set_data (1)
+	wdt_set_count (0)
+	wdt_start ()
+	// Wait for wdt to trigger reboot.
+	while true:
--- a/mips/nanonote/jz4740.hhp
+++ b/mips/nanonote/jz4740.hhp
@@ -22,7 +22,7 @@
 #define __JZ4740_HH__

 // Main clock, for cpu, serial port, and with divisors for most other hardware
-#define JZ_EXTAL	12000000   /* 3.6864 MHz */
+#define JZ_EXTAL	12000000   /* 12 MHz */
 // RTC clock
 #define RTC_CLOCK	32768     /* 32.768 KHz */
 // Interrupt source used for system timer
@@ -50,7 +50,7 @@
 #define	CIM_PHYSICAL	0x13060000
 #define	ETH_PHYSICAL	0x13100000

-#ifdef __KERNEL
+#ifdef __KERNEL__
 // In kernel space you need to add 0xa0000000 to see them unmapped uncached in kseg2.
 #define	CPM_BASE	(0xa0000000 + CPM_PHYSICAL)
 #define	INTC_BASE	(0xa0000000 + INTC_PHYSICAL)
@@ -102,7 +102,7 @@
 #define	ETH_BASE	0x00014000

 // Default lcd framebuffer mapping space.
-#define LCD_FRAMEBUFFER_BASE ((unsigned short *)0x00015000)
+#define LCD_FRAMEBUFFER_BASE ((unsigned char *)0x00015000)

 // Map IO memory (requires a priviledged Kernel::my_thread capability).
 #include <iris.hh>
@@ -2346,17 +2346,18 @@ static void gpio_disable_pull (unsigned p, unsigned pins):
 // CPM
 //**************************************************************************
 static void pll_init ():
-	unsigned PHM_DIV = 3
-	unsigned int cfcr, plcr1
-	int n2FR[33] = { 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 9 }
-	int nf, pllout2;
-	cfcr = CPM_CPCCR_CLKOEN | (n2FR[1] << CPM_CPCCR_CDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT)
-	pllout2 = (cfcr & CPM_CPCCR_PCS) ? 252000000 : (252000000 / 2)
-	CPM_UHCCDR = pllout2 / 48000000 - 1
-	nf = 252000000 * 2 / JZ_EXTAL
-	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN
-	CPM_CPCCR = cfcr
-	CPM_CPPCR = plcr1
+	// The cpu clock is set to 252 MHz
+	unsigned const cpu_clock = 252000000
+	// The usb clock must be 48 MHz
+	unsigned const usb_clock = 48000000
+	// ssi clock must be 12 MHz, therefore it is taken directly from JZ_EXTAL, not from divided pll output.
+
+	// USB clock must be 48 MHz.
+	CPM_UHCCDR = (cpu_clock / 2) / usb_clock - 1
+	// Set up dividers; see documentation for the meaning of all the values.
+	CPM_CPCCR = CPM_CPCCR_CLKOEN | CPM_CPCCR_UCS | (0 << CPM_CPCCR_CDIV_BIT) | (2 << CPM_CPCCR_HDIV_BIT) | (2 << CPM_CPCCR_PDIV_BIT) | (2 << CPM_CPCCR_MDIV_BIT) | (3 << CPM_CPCCR_LDIV_BIT)
+	// Configure the pll frequency to 252 MHz.
+	CPM_CPPCR = ((cpu_clock * 2 / JZ_EXTAL - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN

 static unsigned cpm_get_pllm ():
 	return (CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT
@@ -2388,32 +2389,32 @@ static unsigned cpm_get_uhcdiv ():
 static unsigned cpm_get_ssidiv ():
 	return (CPM_SSICDR & CPM_SSICDR_SSIDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT

-static unsigned cpm_set_cdiv (unsigned v):
-	return CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | (v << (CPM_CPCCR_CDIV_BIT))
-static unsigned cpm_set_hdiv (unsigned v):
-	return CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | (v << (CPM_CPCCR_HDIV_BIT))
-static unsigned cpm_set_pdiv (unsigned v):
-	return CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | (v << (CPM_CPCCR_PDIV_BIT))
-static unsigned cpm_set_mdiv (unsigned v):
-	return CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | (v << (CPM_CPCCR_MDIV_BIT))
-static unsigned cpm_set_ldiv (unsigned v):
-	return CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | (v << (CPM_CPCCR_LDIV_BIT))
-static unsigned cpm_set_udiv (unsigned v):
-	return CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | (v << (CPM_CPCCR_UDIV_BIT))
-static unsigned cpm_set_i2sdiv (unsigned v):
-	return CPM_I2SCDR = (CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | (v << (CPM_I2SCDR_I2SDIV_BIT))
-static unsigned cpm_set_pixdiv (unsigned v):
-	return CPM_LPCDR = (CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | (v << (CPM_LPCDR_PIXDIV_BIT))
-static unsigned cpm_set_mscdiv (unsigned v):
-	return CPM_MSCCDR = (CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | (v << (CPM_MSCCDR_MSCDIV_BIT))
-static unsigned cpm_set_uhcdiv (unsigned v):
-	return CPM_UHCCDR = (CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | (v << (CPM_UHCCDR_UHCDIV_BIT))
-static unsigned cpm_ssiclk_select_exclk ():
-	return CPM_SSICDR &= ~CPM_SSICDR_SCS
-static unsigned cpm_ssiclk_select_pllout ():
-	return CPM_SSICDR |= CPM_SSICDR_SCS
-static unsigned cpm_set_ssidiv (unsigned v):
-	return CPM_SSICDR = (CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT))
+static void cpm_set_cdiv (unsigned v):
+	CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | (v << (CPM_CPCCR_CDIV_BIT))
+static void cpm_set_hdiv (unsigned v):
+	CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | (v << (CPM_CPCCR_HDIV_BIT))
+static void cpm_set_pdiv (unsigned v):
+	CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | (v << (CPM_CPCCR_PDIV_BIT))
+static void cpm_set_mdiv (unsigned v):
+	CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | (v << (CPM_CPCCR_MDIV_BIT))
+static void cpm_set_ldiv (unsigned v):
+	CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | (v << (CPM_CPCCR_LDIV_BIT))
+static void cpm_set_udiv (unsigned v):
+	CPM_CPCCR = (CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | (v << (CPM_CPCCR_UDIV_BIT))
+static void cpm_set_i2sdiv (unsigned v):
+	CPM_I2SCDR = (CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | (v << (CPM_I2SCDR_I2SDIV_BIT))
+static void cpm_set_pixdiv (unsigned v):
+	CPM_LPCDR = (CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | (v << (CPM_LPCDR_PIXDIV_BIT))
+static void cpm_set_mscdiv (unsigned v):
+	CPM_MSCCDR = (CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | (v << (CPM_MSCCDR_MSCDIV_BIT))
+static void cpm_set_uhcdiv (unsigned v):
+	CPM_UHCCDR = (CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | (v << (CPM_UHCCDR_UHCDIV_BIT))
+static void cpm_ssiclk_select_exclk ():
+	CPM_SSICDR &= ~CPM_SSICDR_SCS
+static void cpm_ssiclk_select_pllout ():
+	CPM_SSICDR |= CPM_SSICDR_SCS
+static void cpm_set_ssidiv (unsigned v):
+	CPM_SSICDR = (CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT))

 #define cpm_select_i2sclk_exclk()	(CPM_CPCCR &= ~CPM_CPCCR_I2CS)
 #define cpm_select_i2sclk_pll()	(CPM_CPCCR |= CPM_CPCCR_I2CS)
@@ -2485,7 +2486,7 @@ static unsigned cpm_get_pllout ():
 		m = cpm_get_pllm () + 2
 		n = cpm_get_plln () + 2
 		no = od[cpm_get_pllod ()]
-		pllout = ((JZ_EXTAL) / (n * no)) * m
+		pllout = JZ_EXTAL * m / n / no
 	else:
 		pllout = JZ_EXTAL
 	return pllout
@@ -3011,6 +3012,13 @@ static void ac97_cold_reset_codec():

 #define i2s_reset_codec()			do {						} while (0)

+static void aic_use_internal_codec ():
+	aic_internal_codec ()
+	aic_select_i2s ()
+	i2s_as_slave ()
+	i2s_select_i2s ()
+	cpm_select_i2sclk_exclk ()
+	cpm_set_i2sdiv (1)

 //**************************************************************************
 // ICDC
@@ -3598,8 +3606,8 @@ static void setup_sdram ():
 	unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT }
 	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}

-	cpu_clk = 225000000
-	gpio_as_sdram_32bit ()
+	cpu_clk = 252000000
+	gpio_as_sdram_16bit ()
 	unsigned SDRAM_BW16 = 0
 	unsigned SDRAM_BANK4 = 1
 	unsigned SDRAM_ROW = 13
--- a/mips/nanonote/sdram-setup.ccp
+++ b/mips/nanonote/sdram-setup.ccp
@@ -17,7 +17,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.

 // This runs like the kernel.  In particular, it doesn't want userspace declarations.
-#define __KERNEL
+#define __KERNEL__
 #include "jz4740.hh"

 asm volatile (".set noreorder\n"
--- a/mips/nanonote/threadlist.S
+++ b/mips/nanonote/threadlist.S
@@ -21,25 +21,29 @@

 	.balign 0x1000
 thread0:
-	.incbin "init"
+	.incbin "init.elf"

 	.balign 0x1000
 thread1:
-	.incbin "udc"
+	.incbin "udc.elf"

 	.balign 0x1000
 thread2:
-	.incbin "nanonote-gpio"
+	.incbin "nanonote-gpio.elf"

 	.balign 0x1000
 thread3:
-	.incbin "buzzer"
+	.incbin "buzzer.elf"

 	.balign 0x1000
 thread4:
-	.incbin "metronome"
+	.incbin "metronome.elf"

+	.balign 0x1000
 thread5:
+	.incbin "lcd.elf"
+
+thread6:

 // Everything from here may be freed after kernel initialization.
 init_start:
@@ -51,3 +55,4 @@ thread_start:
 	.word thread3
 	.word thread4
 	.word thread5
+	.word thread6
--- a/mips/trendtac/Makefile.arch
+++ b/mips/trendtac/Makefile.arch
@@ -17,25 +17,25 @@

 load = 0x80000000

-ARCH_CXXFLAGS = -DNUM_THREADS=3
-ARCH_CPPFLAGS = -Imips -Wa,-mips32
+ARCH_CXXFLAGS = -DNUM_THREADS=3 -DTRENDTAC
+ARCH_CPPFLAGS = -I. -Imips -Imips/trendtac -Wa,-mips32
 CROSS = mipsel-linux-gnu-
 OBJDUMP = $(CROSS)objdump
 junk = mdebug.abi32 reginfo comment pdr
 OBJCOPYFLAGS = $(addprefix --remove-section=.,$(junk))

 arch_iris_sources = mips/interrupts.cc mips/arch.cc
-boot_sources = mips/init.cc
-arch_headers = mips/arch.hh mips/jz4730.hh
+boot_sources = mips/init.cc mips/trendtac/board.cc
+arch_headers = mips/arch.hh mips/trendtac/jz4730.hh mips/trendtac/board.hh
 boot_threads = init gpio lcd

 uimage:

-mips/boot.o: TARGET_FLAGS = -DMEMORY_SIZE = "128 << 20"
-mips/threadlist.o: $(boot_threads)
+mips/boot.o: TARGET_FLAGS = -DMEMORY_SIZE="128 << 20"
+mips/trendtac/threadlist.o: $(addsuffix .elf,$(boot_threads))
 mips/init.o: TARGET_FLAGS = -I/usr/include
-$(boot_threads): TARGET_FLAGS = -I.
-$(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): boot-programs/devices.hh boot-programs/init.hh
+$(addsuffix .elf,$(boot_threads)): TARGET_FLAGS = -I.
+$(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): devices.hh
 lcd: boot-programs/charset.data

 boot-programs/charset.data: boot-programs/charset
@@ -58,4 +58,4 @@ iris: mips/entry.o $(subst .cc,.o,$(iris_sources)) mips/trendtac/threadlist.o mi
 %.gz: %
 	gzip < $< > $@

-ARCH_CLEAN_FILES = uimage $(boot_threads) mips/*.o boot-programs/charset.data iris iris.raw iris.raw.gz
+ARCH_CLEAN_FILES = uimage $(addsuffix .elf,$(boot_threads)) mips/*.o boot-programs/charset.data iris iris.raw iris.raw.gz
--- a/mips/trendtac/board.ccp
+++ b/mips/trendtac/board.ccp
@@ -16,6 +16,10 @@
 // You should have received a copy of the GNU General Public License
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.

+#define ARCH
+#define INIT
+#include "kernel.hh"
+
 void board_init ():
 	// Disable all gpio interrupts and alternate functions initially.
 	for unsigned i = 0; i < 4; ++i:
@@ -54,3 +58,12 @@ void board_init ():
 	ost_set_count (0, 1)
 	ost_set_mode (0, OST_TCSR_UIE | OST_TCSR_CKS_EXTAL)
 	ost_enable_channel (0)
+
+void arch_reboot ():
+	// Wait for serial port to be done.
+	while !(UART0_LSR & UARTLSR_TEMT):
+	// Reboot.
+	wdt_set_count (~0)
+	wdt_start ()
+	// Wait for wdt to trigger reboot.
+	while true:
--- a/mips/trendtac/board.hhp
+++ b/mips/trendtac/board.hhp
@@ -0,0 +1,19 @@
+#pypp 0
+// Iris: micro-kernel for a capability-based operating system.
+// mips/trendtac/board.hhp: nanonote-specific declarations and type definitions.
+// Copyright 2009 Bas Wijnen <wijnen@debian.org>
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+#include "jz4730.hh"
--- a/mips/trendtac/jz4730.hhp
+++ b/mips/trendtac/jz4730.hhp
@@ -62,7 +62,7 @@
 #define	UPRT_PHYSICAL	0x10061000
 #define KBC_PHYSICAL	0x10062000

-#ifdef __KERNEL
+#ifdef __KERNEL__
 // In kernel space you need to add 0xa0000000 to see them unmapped uncached in kseg2.
 #define	HARB_BASE	(HARB_PHYSICAL + 0xa0000000)
 #define	EMC_BASE	(EMC_PHYSICAL + 0xa0000000)
@@ -2324,7 +2324,7 @@ static __inline__ void udelay (unsigned us):
 		for unsigned k = 0; k < 100; ++k:
 			GPIO_GPDR (0) = GPIO_GPDR (0)

-#ifndef __KERNEL
+#ifndef __KERNEL__
 static __inline__ void cdelay (unsigned ds):
 	Kernel::my_receiver.set_alarm (ds * (HZ / 100))
 	Kernel::Cap ().call (~0)
@@ -3029,7 +3029,7 @@ static __inline__ void gpio_as_cim ():
 #define i2c_read()		( I2C_DR )
 #define i2c_write(val)	( I2C_DR = (val) )

-#ifndef __KERNEL
+#ifndef __KERNEL__
 static __inline__ void i2c_open ():
 	i2c_set_clk (JZ_EXTAL, 10000)
 	i2c_enable ()
--- a/mips/trendtac/threadlist.S
+++ b/mips/trendtac/threadlist.S
@@ -21,15 +21,15 @@

 	.balign 0x1000
 thread0:
-	.incbin "init"
+	.incbin "init.elf"

 	.balign 0x1000
 thread1:
-	.incbin "lcd"
+	.incbin "lcd.elf"

 	.balign 0x1000
 thread2:
-	.incbin "gpio"
+	.incbin "gpio.elf"

 thread3: