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git://projects.qi-hardware.com/iris.git
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This commit is contained in:
Bas Wijnen
@@ -17,7 +17,7 @@
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load = 0x80000000
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ARCH_CXXFLAGS = -DNUM_THREADS=1
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ARCH_CXXFLAGS = -DNUM_THREADS=3
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ARCH_CPPFLAGS = -Imips -Wa,-mips32
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CROSS = mipsel-linux-gnu-
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OBJDUMP = $(CROSS)objdump
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@@ -26,9 +26,8 @@ OBJCOPYFLAGS = $(addprefix --remove-section=.,$(junk))
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arch_kernel_sources = mips/interrupts.cc mips/test.cc mips/arch.cc
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boot_sources = mips/init.cc
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BUILT_SOURCES = $(kernel_sources) $(boot_sources)
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arch_headers = mips/arch.hh mips/jz4730.hh
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boot_threads = gpio lcd
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boot_threads = init gpio lcd
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uimage:
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@@ -36,6 +35,10 @@ mips/entry.o: $(boot_threads)
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mips/init.o: TARGET_FLAGS = -I/usr/include
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$(boot_threads): TARGET_FLAGS = -I.
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$(boot_threads): boot-programs/devices.hh
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lcd: boot-programs/charset.data
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boot-programs/charset.data: boot-programs/charset
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$< > $@
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# Transform ':' into ';' so vim doesn't think there are errors.
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uimage: kernel.raw.gz Makefile mips/Makefile.arch
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@@ -54,4 +57,4 @@ kernel: mips/entry.o $(subst .cc,.o,$(kernel_sources)) mips/boot.o $(subst .cc,.
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%.gz: %
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gzip < $< > $@
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ARCH_CLEAN_FILES = uimage kernel kernel.raw kernel.raw.gz $(boot_threads) mips/*.o
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ARCH_CLEAN_FILES = uimage kernel kernel.raw kernel.raw.gz $(boot_threads) mips/*.o boot-programs/charset.data
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@@ -54,11 +54,7 @@ void Thread_arch_receive (Thread *thread, unsigned protected_data, Capability::C
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thread->arch.t1 = c->data[1]
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thread->arch.t2 = c->data[2]
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thread->arch.t3 = c->data[3]
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thread->arch.v1 = protected_data
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thread->arch.v0 = 1
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void Thread_arch_receive_fail (Thread *thread):
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thread->arch.v0 = 0
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thread->arch.v0 = protected_data
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unsigned *Thread_arch_info (Thread *thread, unsigned num):
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switch num:
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10
mips/boot.S
10
mips/boot.S
@@ -38,7 +38,14 @@ start_hack_for_disassembler:
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la $sp, kernel_stack + KERNEL_STACK_SIZE
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// TODO: flush cache and optionally refill it.
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// Flush cache.
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lui $v1, 0x8000
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ori $v0, $v1, 0x8000
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1:
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cache 0, 0($v1)
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cache 1, 0($v1)
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bne $v1, $v0, 1b
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addiu $v1, $v1, 32
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// Set kseg0 cachable.
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li $k0, 0x3
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@@ -67,3 +74,4 @@ thread_start:
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.word thread0
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.word thread1
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.word thread2
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.word thread3
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@@ -231,10 +231,14 @@ save_regs:
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.globl thread0
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.globl thread1
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.globl thread2
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.globl thread3
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.balign 0x1000
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thread0:
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.incbin "lcd"
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.incbin "init"
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.balign 0x1000
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thread1:
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.incbin "gpio"
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.incbin "lcd"
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.balign 0x1000
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thread2:
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.incbin "gpio"
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thread3:
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@@ -141,6 +141,8 @@ static void init_threads ():
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//bool executable = shdr->sh_flags & SHF_EXEC_INSTR
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if shdr->sh_type != SHT_NOBITS:
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unsigned file_offset = shdr->sh_offset >> PAGE_BITS
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if ((file_offset + shdr->sh_size) >> PAGE_BITS) >= (PAGE_SIZE >> 2):
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panic (0x87446809, "initial thread too large")
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for unsigned p = (shdr->sh_addr & PAGE_MASK); p < shdr->sh_addr + shdr->sh_size; p += PAGE_SIZE:
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unsigned section_offset = (p - (shdr->sh_addr & PAGE_MASK)) >> PAGE_BITS
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unsigned idx = file_offset + section_offset
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@@ -238,11 +240,9 @@ void init (unsigned mem):
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// Set up initial threads.
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init_threads ()
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// Disable all gpio pins initially.
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// Disable all gpio interrupts and alternate functions initially.
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for unsigned i = 0; i < 4; ++i:
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GPIO_GPIER (i) = 0
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GPIO_GPDIR (i) = 0
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GPIO_GPPUR (i) = 0
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GPIO_GPALR (i) = 0
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GPIO_GPAUR (i) = 0
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// Set up the rest of the hardware (copied from Linux).
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@@ -19,6 +19,11 @@
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#define ARCH
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#include "../kernel.hh"
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typedef unsigned cacheline[8]
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void arch_flush_cache ():
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for cacheline *line = (cacheline *)0x80000000; line < (cacheline *)0x80008000; ++line:
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__asm__ volatile ("lw $k0, %0; cache 0, 0($k0); cache 1, 0($k0)" :: "m"(line))
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static void handle_exit (Thread *old_current):
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if !current || (current == &idle):
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schedule ()
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@@ -26,6 +31,7 @@ static void handle_exit (Thread *old_current):
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current = &idle
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if old_current == current:
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return
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arch_flush_cache ()
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if current != &idle:
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if (Memory *)asids[current->address_space->arch.asid] != current->address_space:
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if asids[0]:
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@@ -146,40 +152,48 @@ Thread *exception ():
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switch (cause >> 2) & 0x1f:
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case 0:
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// Interrupt. This shouldn't happen, since CAUSE[IV] == 1.
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panic (0x11223344, "Interrupt on exception vector.")
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panic (0x01223344, "Interrupt on exception vector.")
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case 1:
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// TLB modification.
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panic (0x21223344, "TLB modification.")
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panic (0x11223344, "TLB modification.")
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case 2:
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// TLB load or instruction fetch.
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (a)
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panic (0x31223344, "TLB load or instruction fetch.")
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panic (0x21223344, "TLB load or instruction fetch.")
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case 3:
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// TLB store.
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (a)
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panic (0x41223344, "TLB store.")
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cp0_get (CP0_BAD_V_ADDR, a)
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dbg_send (a)
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panic (0x31223344, "TLB store.")
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case 4:
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// Address error load or instruction fetch.
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (a)
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panic (0x51223344, "Address error load or instruction fetch.")
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cp0_get (CP0_BAD_V_ADDR, a)
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dbg_send (a)
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panic (0x41223344, "Address error load or instruction fetch.")
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case 5:
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// Address error store.
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dbg_send (current->arch.v1, 4)
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (*(unsigned *)(a & ~3), 32)
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dbg_send (a, 32)
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cp0_get (CP0_BAD_V_ADDR, a)
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dbg_send (a, 32)
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panic (0x61223344, "Address error store.")
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panic (0x51223344, "Address error store.")
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case 6:
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// Bus error instruction fetch.
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panic (0x71223344, "Bus error instruction fetch.")
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panic (0x61223344, "Bus error instruction fetch.")
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case 7:
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// Bus error load or store.
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panic (0x81223344, "Bus error load or store.")
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panic (0x71223344, "Bus error load or store.")
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case 8:
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// Syscall.
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current->pc += 4
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@@ -202,13 +216,13 @@ Thread *exception ():
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panic (0xc1223344, "Arithmetic overflow.")
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case 13:
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// Trap.
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panic (0xe1223344, "Trap.")
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panic (0xd1223344, "Trap.")
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case 15:
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// Floating point exception.
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panic (0xf1223344, "Floating point exception.")
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panic (0xe1223344, "Floating point exception.")
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case 23:
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// Reference to WatchHi/WatchLo address.
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panic (0xf2223344, "Reference to WatchHi/WatchLo address.")
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panic (0xf1223344, "Reference to WatchHi/WatchLo address.")
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case 24:
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// Machine check.
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panic (0xf3223344, "Machine check.")
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