Looking for the lcd problem and more

mips/nanonote/Makefile.arch

@@ -45,13 +45,13 @@ nanonote-boot: mips/nanonote/nanonote-boot.cc mips/nanonote/sdram-setup.raw
 
 mips/nanonote/sdram-setup.elf: mips/nanonote/sdram-setup.ld
 mips/nanonote/sdram-setup.elf: LDFLAGS = --omagic -T mips/nanonote/sdram-setup.ld
+mips/nanonote/threadlist.o: $(addsuffix .elf,$(boot_threads))
 mips/boot.o: TARGET_FLAGS = -DMEMORY_SIZE="32 << 20"
-mips/entry.o: $(addsuffix .elf,$(boot_threads))
 mips/init.o: TARGET_FLAGS = -I/usr/include
 $(addsuffix .elf,$(boot_threads)): TARGET_FLAGS = -I.
 $(addsuffix .elf,$(boot_threads)): LDFLAGS = -EL
 $(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): devices.hh keys.hh
-lcd: boot-programs/charset.data
+lcd.elf: boot-programs/charset.data
 
 boot-programs/charset.data: boot-programs/charset
 	$< > $@
@@ -64,3 +64,5 @@ iris.elf: mips/entry.o $(subst .cc,.o,$(iris_sources)) mips/nanonote/threadlist.
 	$(LD) $(LDFLAGS) $^ -o $@
 
 ARCH_CLEAN_FILES = $(boot_sources) $(addsuffix .elf,$(boot_threads)) $(arch_headers) devices.hh keys.hh mips/*.o mips/nanonote/*.o boot-programs/charset.data iris.elf iris.raw mips/nanonote/sdram-setup.elf mips/nanonote/sdram-setup.raw
+
+.PRECIOUS: mips/arch.hh mips/nanonote/jz4740.hh mips/nanonote/board.hh 

mips/nanonote/board.ccp

@@ -21,14 +21,21 @@
 #include "kernel.hh"
 
 void board_init ():
+	unsigned cpm_uhccdr = CPM_UHCCDR
+	unsigned cpm_cpccr = CPM_CPCCR
+	unsigned cpm_cppcr = CPM_CPPCR
 	pll_init ()
-	cpm_start_all ()
+	cpm_stop_all ()
+	cpm_start_uart0 ()
+	cpm_start_tcu ()
+	cpm_start_lcd ()
 	gpio_as_uart0 ()
 	gpio_as_sdram_16bit ()
 	gpio_as_nand ()
 	gpio_as_aic ()
 	gpio_as_msc ()
 	gpio_as_lcd_16bit ()
+	gpio_as_pwm4 ()
 	// Set up memory.
 	setup_sdram ()
 	// Use some gpio pins for lcd.
@@ -38,6 +45,7 @@ void board_init ():
 	gpio_as_output (3, 1 << 27)
 	// Set up keyboard: this breaks uart receive.
 	gpio_as_gpio (3, 0x05fc0000)
+	// Set up timed interrupts.
 	tcu_stop_counter (0)
 	tcu_select_extalclk (0)
 	tcu_select_clk_div4 (0)
@@ -62,6 +70,10 @@ void board_init ():
 	UART0_FCR = UARTFCR_UUE | UARTFCR_FE | UARTFCR_RFLS | UARTFCR_TFLS
 	dbg_code.l = 1
 	dbg_log ("Serial port initialized\n")
+	dbg_log_num (CPM_CPCCR)
+	dbg_log ("+")
+	dbg_log_num (CPM_CPPCR)
+	dbg_log ("\n")
 
 void arch_reboot ():
 	// Wait for serial port to be done.

mips/nanonote/jz4740.hhp

@@ -2346,18 +2346,16 @@ static void gpio_disable_pull (unsigned p, unsigned pins):
 // CPM
 //**************************************************************************
 static void pll_init ():
-	// The cpu clock is set to 252 MHz
-	unsigned const cpu_clock = 252000000
-	// The usb clock must be 48 MHz
-	unsigned const usb_clock = 48000000
-	// ssi clock must be 12 MHz, therefore it is taken directly from JZ_EXTAL, not from divided pll output.
-
-	// USB clock must be 48 MHz.
-	CPM_UHCCDR = (cpu_clock / 2) / usb_clock - 1
-	// Set up dividers; see documentation for the meaning of all the values.
-	CPM_CPCCR = CPM_CPCCR_CLKOEN | CPM_CPCCR_UCS | (0 << CPM_CPCCR_CDIV_BIT) | (2 << CPM_CPCCR_HDIV_BIT) | (2 << CPM_CPCCR_PDIV_BIT) | (2 << CPM_CPCCR_MDIV_BIT) | (3 << CPM_CPCCR_LDIV_BIT)
-	// Configure the pll frequency to 252 MHz.
+	// The cpu clock frequency
+	//unsigned const cpu_clock = 336000000
+	unsigned const cpu_clock = 210000000
+	unsigned const pixclock = 27000000
+	// Configure the pll frequency to cpu_clock.
 	CPM_CPPCR = ((cpu_clock * 2 / JZ_EXTAL - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN
+	// Set up dividers; see documentation for the meaning of all the values.
+	// USB clock seems to work when bypassing the pll. (even though it must be 48 MHz according to the datasheet.)
+	CPM_CPCCR = CPM_CPCCR_CLKOEN | (0 << CPM_CPCCR_CDIV_BIT) | (2 << CPM_CPCCR_HDIV_BIT) | (2 << CPM_CPCCR_PDIV_BIT) | (2 << CPM_CPCCR_MDIV_BIT) | (3 << CPM_CPCCR_LDIV_BIT) | CPM_CPCCR_CE | CPM_CPCCR_PCS
+	CPM_LPCDR = (cpu_clock / pixclock) - 1
 
 static unsigned cpm_get_pllm ():
 	return (CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT
@@ -3584,7 +3582,7 @@ static void cim_enable_nongated_clock_mode ():
 #define rtc_set_scratch_pattern(n) 		(RTC_HSPR = n )
 
 
-
+#ifdef __KERNEL__
 static void setup_sdram ():
 	// SDRAM BANK Number: 1, 2
 	unsigned CONFIG_NR_DRAM_BANKS = 1
@@ -3682,6 +3680,31 @@ static void setup_sdram ():
 
 	// Set back to basic DMCR value
 	EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET
-
+	#if 0
+	EMC_SMCR (0) = 0x00000080
+	EMC_SMCR (1) = 0x094c4400
+	EMC_SMCR (2) = 0x0fff7700
+	EMC_SMCR (3) = 0x0fff7700
+	EMC_SMCR (4) = 0x0fff7700
+	EMC_SACR (0) = 0x1cfc
+	EMC_SACR (1) = 0x18fc
+	EMC_SACR (2) = 0x14fc
+	EMC_SACR (3) = 0x0cfc
+	EMC_SACR (4) = 0x08fc
+	EMC_DMCR = 0x85aa3211
+	EMC_RTCSR = 0x83
+	EMC_RTCOR = 0x1f
+	#endif
+	for unsigned i = 0; i < 5; ++i:
+		dbg_log ("memory: ")
+		dbg_log_num (EMC_SMCR (i), 8)
+		dbg_log (",")
+		dbg_log_num (EMC_SACR (i), 8)
+		dbg_log (";")
+	dbg_log_num (EMC_RTCSR, 8)
+	dbg_log (",")
+	dbg_log_num (EMC_RTCOR, 8)
+	dbg_log ("\n")
+#endif
 
 #endif

mips/nanonote/nanonote-boot.ccp

@@ -135,7 +135,7 @@ nanonote::nanonote (unsigned skip):
 	// Get info will reset the device if it has already booted into Iris.
 	get_cpu_info ()
 	usb_close (handle)
-	sleep (1)
+	sleep (5)
 	if !find_device (skip):
 		std::cerr << "unable to find NanoNote device again.\n";
 		throw "unable to find NanoNote device again";

mips/nanonote/sdram-setup.ccp

@@ -18,6 +18,9 @@
 
 // This runs like the kernel.  In particular, it doesn't want userspace declarations.
 #define __KERNEL__
+#define dbg_log(x) do {} while (0)
+#define dbg_log_char(x) do {} while (0)
+#define dbg_log_num(...) do {} while (0)
 #include "jz4740.hh"
 
 asm volatile (".set noreorder\n"

mips/nanonote/threadlist.S

@@ -25,7 +25,7 @@ thread0:
 
 	.balign 0x1000
 thread1:
-	.incbin "udc.elf"
+	.incbin "lcd.elf"
 
 	.balign 0x1000
 thread2:
@@ -41,7 +41,7 @@ thread4:
 
 	.balign 0x1000
 thread5:
-	.incbin "lcd.elf"
+	.incbin "udc.elf"
 
 thread6: