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Makefile.am
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@ -27,29 +27,29 @@ objcopyflags = -S $(addprefix --remove-section=.,$(junk))
start_load = 0x80003000
load = 0x80000000
noinst_DATA = iris.raw mips/start.raw mips/start-hack.S mips/nanonote/sdram-setup.raw
noinst_PROGRAMS = iris.elf mips/start.elf mips/nanonote/sdram-setup.elf
noinst_DATA = iris.raw mips/start.raw mips/start-hack.S mips/board/sdram-setup.raw
noinst_PROGRAMS = iris.elf mips/start.elf mips/board/sdram-setup.elf
%.raw: %.elf
$(OBJCOPY) $(objcopyflags) -Obinary $< $@
# Define boot_threads depending on selected mode.
if UDC
boot_threads = udc
boot_threads = hardware/udc
else
if UNBRICK
boot_threads = sdmmc usbmassstorage
boot_threads = hardware/sdmmc glue/usbmassstorage
else
boot_threads = sdmmc partition fat
boot_threads = hardware/sdmmc glue/partition glue/fat
noinst_DATA += iris.tar.gz
endif
endif
# Threadlist must be the last file on the line below.
iris_sources = panic.cc data.cc alloc.cc memory.cc invoke.cc schedule.cc mips/interrupts.cc mips/arch.cc threadlist.S
boot_sources = mips/init.cc mips/nanonote/board.cc
headers = kernel.hh iris.hh devices.hh ui.hh keys.hh mips/arch.hh mips/nanonote/jz4740.hh mips/nanonote/board.hh mips/nand.hh
iris_elf_CPPFLAGS = -O5 -fno-inline -I. -Imips -Imips/nanonote -Wa,-mips32 -DNANONOTE -DUSE_SERIAL
iris_sources = kernel/panic.cc kernel/data.cc kernel/alloc.cc kernel/memory.cc kernel/invoke.cc kernel/schedule.cc mips/interrupts.cc mips/arch.cc source/boot/threadlist.S
boot_sources = mips/init.cc mips/board/board.cc
headers = include/kernel.hh include/iris.hh include/devices.hh include/ui.hh include/keys.hh mips/arch.hh mips/board/jz4740.hh mips/board/board.hh mips/nand.hh
iris_elf_CPPFLAGS = -O5 -fno-inline -Iinclude -Imips -Imips/board -Wa,-mips32 -DNANONOTE -DUSE_SERIAL
iris_elf_CXXFLAGS = -Wno-unused-parameter -fno-strict-aliasing -fno-builtin -ggdb3
iris_elf_LDFLAGS = -Wl,--omagic -Wl,-Ttext -Wl,$(load) -nostdlib
iris_elf_SOURCES = mips/entry.S ${iris_sources} mips/boot.S ${boot_sources} ${headers}
@ -61,35 +61,35 @@ mips_start_elf_SOURCES = mips/start-hack.S iris.raw
mips/start-hack.S: mips/start.S iris.raw
cp $< $@
mips_nanonote_sdram_setup_elf_DEPENDENCIES = mips/nanonote/sdram-setup.ld
mips_nanonote_sdram_setup_elf_CPPFLAGS = -O5 -fno-inline -I. -Imips -Imips/nanonote -Wa,-mips32
mips_nanonote_sdram_setup_elf_CXXFLAGS = -Wno-unused-parameter -fno-strict-aliasing -fno-builtin -ggdb3
mips_nanonote_sdram_setup_elf_LDFLAGS = -Wl,--omagic -Wl,-T -Wl,mips/nanonote/sdram-setup.ld -nostdlib
mips_nanonote_sdram_setup_elf_SOURCES = mips/nanonote/sdram-setup.cc
mips_board_sdram_setup_elf_DEPENDENCIES = mips/board/sdram-setup.ld
mips_board_sdram_setup_elf_CPPFLAGS = -O5 -fno-inline -Iinclude -Imips -Imips/board -Wa,-mips32
mips_board_sdram_setup_elf_CXXFLAGS = -Wno-unused-parameter -fno-strict-aliasing -fno-builtin -ggdb3
mips_board_sdram_setup_elf_LDFLAGS = -Wl,--omagic -Wl,-T -Wl,mips/board/sdram-setup.ld -nostdlib
mips_board_sdram_setup_elf_SOURCES = mips/board/sdram-setup.cc
program_targets = \
source/alarm.elf \
source/ball.elf \
source/boot.elf \
source/booter.elf \
source/bootinit.elf \
source/bsquare.elf \
source/buzzer.elf \
source/init.elf \
source/boot.elf \
source/gpio.elf \
source/lcd.elf \
source/nand.elf \
source/rtc.elf \
source/sdmmc.elf \
source/udc.elf \
source/elfrun.elf \
source/fat.elf \
source/font.elf \
source/gpio.elf \
source/gui.elf \
source/init.elf \
source/lcd.elf \
source/metronome.elf \
source/nand.elf \
source/partition.elf \
source/rtc.elf \
source/sdmmc.elf \
source/test.elf \
source/udc.elf \
source/usbmassstorage.elf
source/usbmassstorage.elf \
source/alarm.elf \
source/ball.elf \
source/booter.elf \
source/bsquare.elf \
source/buzzer.elf \
source/metronome.elf \
source/test.elf
fs_targets = \
fs/alarm.elf \
@ -117,14 +117,14 @@ fs_targets = \
noinst_PROGRAMS += $(program_targets)
noinst_DATA += $(fs_targets)
AM_CPPFLAGS = -O5 -fno-inline -I. -I./mips -I./mips/nanonote -Wa,-mips32 -DNANONOTE
AM_CPPFLAGS = -O5 -fno-inline -Iinclude -Imips -Imips/board -Wa,-mips32 -DNANONOTE
AM_CXXFLAGS = -Wno-unused-parameter -fno-strict-aliasing -fno-builtin -ggdb3
AM_LDFLAGS = -nostdlib
BUILT_SOURCES = $(headers) source/charset.data server
BUILT_SOURCES = $(headers) source/data/charset.data server
threadlist.S: mkthreadlist Makefile $(addprefix fs/,$(addsuffix .elf,bootinit $(boot_threads)))
$(top_srcdir)/$< bootinit $(boot_threads) > $@
source/boot/threadlist.S: source/boot/mkthreadlist Makefile $(addprefix fs/,$(addsuffix .elf,bootinit $(notdir $(boot_threads))))
$< bootinit $(boot_threads) > $@
PYPP = /usr/bin/pypp
%.cc: %.ccp
@ -132,45 +132,50 @@ PYPP = /usr/bin/pypp
%.hh: %.hhp
$(PYPP) --name $< < $< > $@
source/charset.data: source/charset
source/data/charset.data: source/data/charset
$< > $@
fs/font.dat: courier-10+8+32.png makefont
./makefont $< > $@
fs/%: %
fs/font.dat: source/data/courier-10+8+32.png source/data/makefont
source/data/makefont $< > $@
fs/init.config: source/data/init.config
ln -s ../$< $@
fs/%.elf: source/%.elf
mkdir -p fs
$(OBJCOPY) -S $< $@
source_alarm_elf_SOURCES = source/crt0.cc source/alarm.cc ${headers}
source_ball_elf_SOURCES = source/crt0.cc source/ball.cc ${headers}
source_boot_elf_SOURCES = source/crt0.cc source/boot.cc ${headers}
source_booter_elf_SOURCES = source/crt0.cc source/booter.cc ${headers}
source_bootinit_elf_SOURCES = source/crt0.cc source/bootinit.cc ${headers}
source_bsquare_elf_SOURCES = source/crt0.cc source/bsquare.cc ${headers}
source_buzzer_elf_SOURCES = source/crt0.cc source/buzzer.cc ${headers}
source_elfrun_elf_SOURCES = source/crt0.cc source/elfrun.cc ${headers}
source_fat_elf_SOURCES = source/crt0.cc source/fat.cc ${headers}
source_font_elf_SOURCES = source/crt0.cc source/font.cc ${headers}
source_gpio_elf_SOURCES = source/crt0.cc source/gpio.cc ${headers}
source_gui_elf_SOURCES = source/crt0.cc source/gui.cc ${headers}
source_init_elf_SOURCES = source/crt0.cc source/init.cc ${headers}
source_lcd_elf_SOURCES = source/crt0.cc source/lcd.cc ${headers}
source_metronome_elf_SOURCES = source/crt0.cc source/metronome.cc ${headers}
source_nand_elf_SOURCES = source/crt0.cc source/nand.cc ${headers}
source_partition_elf_SOURCES = source/crt0.cc source/partition.cc ${headers}
source_rtc_elf_SOURCES = source/crt0.cc source/rtc.cc ${headers}
source_sdmmc_elf_SOURCES = source/crt0.cc source/sdmmc.cc ${headers}
source_test_elf_SOURCES = source/crt0.cc source/test.cc ${headers}
source_udc_elf_SOURCES = source/crt0.cc source/udc.cc ${headers}
source_usbmassstorage_elf_SOURCES = source/crt0.cc source/usbmassstorage.cc ${headers}
source_bootinit_elf_SOURCES = source/boot/crt0.cc source/boot/bootinit.cc ${headers}
source_init_elf_SOURCES = source/boot/crt0.cc source/boot/init.cc ${headers}
source_boot_elf_SOURCES = source/boot/crt0.cc source/hardware/boot.cc ${headers}
source_buzzer_elf_SOURCES = source/boot/crt0.cc source/hardware/buzzer.cc ${headers}
source_gpio_elf_SOURCES = source/boot/crt0.cc source/hardware/gpio.cc ${headers}
source_lcd_elf_SOURCES = source/boot/crt0.cc source/hardware/lcd.cc ${headers}
source_nand_elf_SOURCES = source/boot/crt0.cc source/hardware/nand.cc ${headers}
source_rtc_elf_SOURCES = source/boot/crt0.cc source/hardware/rtc.cc ${headers}
source_sdmmc_elf_SOURCES = source/boot/crt0.cc source/hardware/sdmmc.cc ${headers}
source_udc_elf_SOURCES = source/boot/crt0.cc source/hardware/udc.cc ${headers}
#source_buffer_elf_SOURCES = source/boot/crt0.cc source/glue/buffer.cc ${headers}
source_elfrun_elf_SOURCES = source/boot/crt0.cc source/glue/elfrun.cc ${headers}
source_fat_elf_SOURCES = source/boot/crt0.cc source/glue/fat.cc ${headers}
source_font_elf_SOURCES = source/boot/crt0.cc source/glue/font.cc ${headers}
source_gui_elf_SOURCES = source/boot/crt0.cc source/glue/gui.cc ${headers}
source_partition_elf_SOURCES = source/boot/crt0.cc source/glue/partition.cc ${headers}
source_usbmassstorage_elf_SOURCES = source/boot/crt0.cc source/glue/usbmassstorage.cc ${headers}
source_metronome_elf_SOURCES = source/boot/crt0.cc source/application/metronome.cc ${headers}
source_test_elf_SOURCES = source/boot/crt0.cc source/application/test.cc ${headers}
source_alarm_elf_SOURCES = source/boot/crt0.cc source/application/alarm.cc ${headers}
source_ball_elf_SOURCES = source/boot/crt0.cc source/application/ball.cc ${headers}
source_booter_elf_SOURCES = source/boot/crt0.cc source/application/booter.cc ${headers}
source_bsquare_elf_SOURCES = source/boot/crt0.cc source/application/bsquare.cc ${headers}
server:
test -e native/Makefile || native/autogen.sh
$(MAKE) -C native
# This target is meaningless for SD boot mode.
test: mips/start.raw mips/start.elf server mips/nanonote/sdram-setup.raw fs/init.config fs/font.dat
test: mips/start.raw mips/start.elf server mips/board/sdram-setup.raw fs/init.config fs/font.dat
echo shutdown | nc localhost 5050 || true
native/usb-server
echo 'reboot $(start_load) 0x$(shell /bin/sh -c '$(OBJDUMP) -t mips/start.elf | grep __start$$ | cut -b1-8') mips/start.raw' | nc localhost 5050
@ -213,4 +218,4 @@ debug:
autoclean: maintainer-clean
$(MAKE) -C native autoclean
rm -rf aclocal.m4 configure depcomp fs install-sh iris.raw iris-sd.tar Makefile.in missing $(iris_sources) $(boot_sources) $(sources) $(headers) mips/start-hack.S mips/start.raw
rm -rf aclocal.m4 configure depcomp fs install-sh iris.raw iris-sd.tar Makefile.in missing $(iris_sources) $(boot_sources) $(sources) $(headers) mips/start-hack.S mips/start.raw mips/start.raw.gz source/data/charset.data iris.tar.gz

37
README.build
View File

@ -1,37 +0,0 @@
Building Iris.
For building, you will need:
- A compiler to create mips binaries. Unless you run on a mips platform, which
is unlikely, that means a cross-compiler.
- The pythonic preprocessor, pypp.
- Python
- mkimage, from the Debian package uboot-mkimage.
The last two can simply be installed using your favorite package manager. For
the cross compiler, please follow the instructions from
report/cross-compiler.tex.
Pypp can be downloaded using
svn co http://a82-93-13-222.adsl.xs4all.nl/svn/trunk/pypp
To build, it needs libshevek, which can be downloaded with
svn co http://a82-93-13-222.adsl.xs4all.nl/svn/trunk/libshevek
For both of them, dpkg-buildpackage -uc -us in their directory creates a Debian
package which can be installed. Install libshevek*deb before building pypp.
If you are not using Debian, use
autoreconf -f -i -s
./configure --prefix=/usr
make
make install
When all is installed, "make" should be enough to create "uimage". To use it,
make the first partition of an SD card (it really must be SD; MMC does not
work) smaller than 32 MB; I use 16 MB myself. Format it as FAT and copy uimage
to it. Then insert it in the Trendtac (it fits upside down) and boot with
Fn+left Ctrl+left Shift pressed. When caps and scroll lock are flashing, Iris
is booting (the flashing lights are from uboot, not from Iris, but they
indicate that the SD image is used). Then you can release the keys.
If anything doesn't work, or you have other comments, please send a message to
Bas Wijnen <wijnen@debian.org>. Thanks.

4
autogen.sh
View File

@ -1,3 +1,7 @@
#!/bin/sh
autoreconf --force --install --symlink
if [ $# -eq 0 ] ; then
./configure --host mipsel-linux-gnu --enable-udc-boot
else
./configure --host mipsel-linux-gnu "$@"
fi

47
clocks.txt
View File

@ -1,47 +0,0 @@
cclk: cpu clock. Fastest clock in the system.
hclk: high-speed peripheral bus clock.
pclk: peripheral bus clock.
mclk: memory clock, for emc.
ldclk: lcd device clock.
lpclk: lcd pixel clock.
cim_mclk: clock output for cim.
cim_pclk: clock input for cim.
i2sclk: codec clock.
mscclk: msc clock.
ssiclk: ssi clock.
exclk: 12MHz clock output, used by uart, i2c, ssi, tcu, usb2.0-phy.
rtclk: 32768Hz clock input for rtc.
cclk: 252M
hclk: 84M
pclk: 84M
mclk: 84M
ldclk: 84M; must not be larger than 150M
lpclk: 25295340 (70Hz screen refresh)
cim_mclk: not used.
cim_pclk: not used.
i2sclk: must be 12M
mscclk: must not be larger than 400k during init; not larger than 25M later.
ssiclk: not used.
exclk: 12M, not adjustable.
rtclk: 32768, not adjustable.
usb clock, for host and device, must be 48M.
restrictions:
- cclk must be i*hclk
- i must not be 24 or 32
- hclk = mclk or hclk = 2*mclk
- mclk = k*pclk
so:
- pclk is set
- mclk = k*pclk
- hclk = l*mclk = l*k*pclk; l = 1 or 2
- cclk = i*hclk = i*l*k*pclk; i != 24 or 32
In the code:
m = 42
n = 2
no = 1
So clkout = 12M * 21 = 252M; this is the pll clock frequency.

0
devices.hhp → include/devices.hhp
View File

0
iris.hhp → include/iris.hhp
View File

0
kernel.hhp → include/kernel.hhp
View File

0
keys.hhp → include/keys.hhp
View File

0
ui.hhp → include/ui.hhp
View File

0
alloc.ccp → kernel/alloc.ccp
View File

0
data.ccp → kernel/data.ccp
View File

0
invoke.ccp → kernel/invoke.ccp
View File

0
memory.ccp → kernel/memory.ccp
View File

0
panic.ccp → kernel/panic.ccp
View File

0
schedule.ccp → kernel/schedule.ccp
View File

89
mbr+fat.txt
View File

@ -1,89 +0,0 @@
mbr structure. Size: 200.
000 1b8 code or fat:
00 3 jump instruction
03 8 OEM name
0b 2 bytes per sector
0d 1 sectors per cluster
0e 2 reserved sectors (incl. boot sector, from boot sector)
10 1 number of fats
11 2 non fat32: number of entries in root directory
13 2 total number of sectors on disk if < 32MB
15 1 media descriptor (bit 2 set means removable)
16 2 non fat32: sectors per fat
18 2 sectors per track
1a 2 heads
1c 4 number of sectors before boot sector
20 4 number of sectors on disk, if > 32MB
24 xx 4 sectors per fat
28 xx 2 bit 0-4: active fat, bit 7 set: write to all fats.
2a xx 2 file system version number
2c xx 4 cluster number for root directory
30 xx 2 sector number for FSInfo structure
32 xx 2 boot sector backup sector
34 xx c reserved
40 24 1 drive number
41 25 1 current head (dos internal)
42 26 1 boot signature (with 0x29, the next 3 fields are valid)
43 27 4 volume id
47 2b b volume label
52 36 8 file system type "FAT16 " / "FAT32 " / ...
1b8 004 disk signature
1bc 002 null
1be 010 partition 0
1ce 010 partition 1
1de 010 partition 2
1ee 010 partition 3
1fe 002 mbr signature: 55 aa.
Partition structure. Size: 10.
0 1 bootable flag 00=no; 80=yes.
1 3 first sector in partition, chs
4 1 partition type
5 3 last sector in partition, chs
8 4 first sector in partition, lba
c 4 number of sectors in partition, for lba
CHS address. Size: 3.
head = chs[0]
sector = chs[1] & 0x3f
cylinder = (chs[1] & 0xc0) << 2 | chs[2]
Fat filesystem information sector. Size: 200.
000 4 signature: 52 52 61 41
004 1e0 unused
1e4 4 fsinfo signature: 72 72 41 61
1e8 4 number of free clusters
1ec 4 most recently allocated cluster
1f0 c reserved
1fc 2 unknown
1fe 2 boot record signature: 55 aa
Directory entry. Size: 20.
00 8 name
08 3 extension
0b 1 attributes (00arshdv)
0c 1 0
0d 1 creation time: (milli?)seconds
0e 2 creation time: hour and minute
10 2 creation date
12 2 last accessed date
14 2 cluster[31:16]
16 2 time
18 2 date
1a 2 cluster[15:0]
1c 4 file size
long file name: stored in directory entries immediately before the 8.3 name (last entry is first part of name)
00 1 ordinal field, bit 6 set means highest.
01 a 5 unicode characters.
0b 1 attribute: 000rsh0v.
0c 1 0
0d 1 checksum of short filename.
0e c 6 unicode characters.
1a 2 0
1c 4 2 unicode characters.
checksum is name[0] rotated 11 times, name[1] 10 times, etc and all added up.

2
mips/arch.ccp
View File

@ -280,7 +280,7 @@ void arch_register_interrupt (unsigned num, kReceiver *r):
// kdebug ("enabled interrupt ")
// kdebug_num (num)
// kdebug (", state: ")
//kdebug_num (INTC_ISR)
// kdebug_num (INTC_IMR)
// kdebug ("\n")
intc_unmask_irq (num)
else:

10
mips/entry.S
View File

@ -30,20 +30,20 @@
#include "arch.hh"
addr_000:
#if 0
#if 1
// TLB refill
lui $k0, 0x8000
lw $k1, 0x174($k0) // directory
mfc0 $k0, $CP0_ENTRY_HI
srl $k0, $k0, 19
and $k0, $k0, 0xffc
andi $k0, $k0, 0xffc
addu $k0, $k0, $k1
beq $zero, $k0, zero_refill
lw $k0, 0($k0)
beq $zero, $k0, zero_refill
mfc0 $k1, $CP0_ENTRY_HI
srl $k1, $k1, 10
and $k1, $k1, 0xff8
add $k0, $k0, $k1
andi $k1, $k1, 0x7f8
addu $k0, $k0, $k1
lw $k1, 0($k0)
mtc0 $k1, $CP0_ENTRY_LO0
lw $k1, 4($k0)

2
mips/init.ccp
View File

@ -20,7 +20,7 @@
// Also declare things which only work during kernel init.
#define INIT
#define ARCH
#include "../kernel.hh"
#include "kernel.hh"
#include <elf.h>
#define NUM_SLOTS 8

18
mips/interrupts.ccp
View File

@ -18,7 +18,7 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
#define ARCH
#include "../kernel.hh"
#include "kernel.hh"
void arch_flush_cache ():
__asm__ volatile ("\t.set noreorder\n"
@ -73,7 +73,6 @@ static kThread *handle_exit ():
/// Otherwise, the ultra-fast code in entry.S is used.
kThread *tlb_refill ():
++dbg_code.h
kdebug_num ((unsigned)directory)
old_current = current
if !directory:
unsigned addr
@ -82,9 +81,6 @@ kThread *tlb_refill ():
return handle_exit ()
unsigned EntryHi
cp0_get (CP0_ENTRY_HI, EntryHi)
kdebug (" tlb ")
kdebug_num (EntryHi)
kdebug ("\n")
Table *t = directory[EntryHi >> 21]
if !t:
unsigned addr
@ -116,15 +112,19 @@ kThread *interrupt ():
++dbg_code.h
old_current = current
unsigned ipr = INTC_IPR
//if ipr & ~((1 << TIMER_INTERRUPT) | (1 << 0x18)):
// kdebug ("interrupt: ")
// kdebug_num (ipr)
// kdebug ("&")
// kdebug_num (~INTC_IMR)
for unsigned i = 0; i < 32; ++i:
if ipr & (1 << i):
// Handle timer interrupts specially: don't disable them.
if i == TIMER_INTERRUPT:
continue
//if i != 0x18:
//kdebug ("interrupt: ")
// kdebug (" ")
// kdebug_num (i, 2)
//kdebug ("\n")
// Disable the interrupt while handling it.
intc_mask_irq (i)
intc_ack_irq (i)
@ -135,6 +135,8 @@ kThread *interrupt ():
c.data[1] = 0
arch_interrupt_receiver[i]->send_message (0, &c)
arch_interrupt_receiver[i] = NULL
//if ipr & ~((1 << TIMER_INTERRUPT) | (1 << 0x18)):
// kdebug ("\n")
if ipr & (1 << TIMER_INTERRUPT):
#if defined (TRENDTAC)
ost_clear_uf (0)
@ -155,7 +157,7 @@ void flush_tlb (unsigned asid):
cp0_get (CP0_ENTRY_HI, hi)
if (hi & 0x1f) == asid:
// Set asid to 0, which is only used by the idle task.
cp0_set (CP0_ENTRY_HI, 0x2000 * tlb)
cp0_set (CP0_ENTRY_HI, 0x2000 * (tlb + 2))
__asm__ volatile ("tlbwi")
static void arch_invoke ():

37
mips/nanonote/board.ccp
View File

@ -23,9 +23,21 @@
void board_init ():
pll_init ()
cpm_start_all ()
// Timer interrupts and buzzer.
cpm_start_tcu ()
// Stop all clocks, except the RTC and timer interrupt source.
CPM_CLKGR = 0x7fff & ~(CPM_CLKGR_RTC | CPM_CLKGR_TCU)
// Make sure the rtc is able to boot the device.
while !rtc_write_ready ():
rtc_enabled ()
while !rtc_write_ready ():
// Set wakeup assertion time, so it actually wakes up.
rtc_set_hrcr_val (0xfe0)
while !rtc_write_ready ():
// Set glitch detection to a low value.
rtc_set_hwfcr_val (0x1e0)
while !rtc_write_ready ():
// Allow rtc alarm to wake up device.
rtc_enable_alarm_wakeup ()
while !rtc_write_ready ():
// sdram memory.
gpio_as_sdram_16bit ()
// flash memory.
@ -86,26 +98,13 @@ void arch_reboot ():
while true:
void arch_poweroff ():
// Power off.
// First enable interrupts, so it can be awoken.
// Disable all interrupts which shouldn't wake it (only an issue while powering down, really).
INTC_IMSR = ~0
intc_unmask_irq (IRQ_RTC)
intc_unmask_irq (IRQ_GPIO3)
GPIO_PXIMS (3) = ~0
gpio_unmask_irq (3, 29)
// Clear interrupt flags.
gpio_ack_irq (3, 29)
intc_ack_irq (IRQ_GPIO3)
intc_ack_irq (IRQ_RTC)
// Clear pending interrupts and enable interrupts.
cp0_set (CP0_STATUS, 0x1000ff01)
// Make sure the rtc is running.
// Make sure the rtc is running; it wakes the device up.
cpm_start_rtc ()
while !rtc_write_ready ():
rtc_enabled ()
while !rtc_write_ready ():
rtc_set_hwfcr_val (0x1e0)
while !rtc_write_ready ():
rtc_set_hrcr_val (0x7f)
while !rtc_write_ready ():
kdebug ("Power down.\n")

2
native/Makefile.am
View File

@ -20,7 +20,7 @@ AUTOMAKE_OPTIONS = foreign
bin_PROGRAMS = usb-server
usb_server_SOURCES = usb-server.cc
usb_server_CPPFLAGS = $(SHEVEK_CFLAGS) -DSTAGE1_FILE=\"mips/nanonote/sdram-setup.raw\" -I.. -DCOPYRIGHT_YEARS=\"2009-2012\" -DCOPYRIGHT_AUTHOR=\"Bas\ Wijnen\" -DCOPYRIGHT_EMAIL=\"wijnen@debian.org\"
usb_server_CPPFLAGS = $(SHEVEK_CFLAGS) -DSTAGE1_FILE=\"mips/nanonote/sdram-setup.raw\" -I../include -DCOPYRIGHT_YEARS=\"2009-2012\" -DCOPYRIGHT_AUTHOR=\"Bas\ Wijnen\" -DCOPYRIGHT_EMAIL=\"wijnen@debian.org\"
usb_server_LDFLAGS = $(SHEVEK_LIBS) -lusb
PYPP = /usr/bin/pypp

125
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@ -1,125 +0,0 @@
caps zonder size limit?
invoke ipc: try sync; try receiver memory; try caller memory; fail.
memories map:
top
- lcd
- keyboard
- sound
- led
- udc
- battery
- beeper
- msc
- nand
- filesystem
- network
- top session manager
- - user session
- - - program container
- - - - driver emulation
- - - - driver emulation
- - - - program
- - - program container
- - - - driver emulation
- - - - program
- - user session
...
te doen:
- caps in init met een cap per process
- die cap bevat caps in target memory met een cap per service
- die cap bevat een user van de service
- sysreq is geen aangeboden service, usbfs wel
- sysreq schakelt tussen running processes incl. user switching.
- display interface: put pixel commando
- typewriter: print toetsen op scherm; shell?
- terminal
- emulaties automatisch per proces
- start programma van filesystem
- nand driver
- filesystems met backing store
Boot process:
- bootinit and filesystem (and backing store) are started.
- bootinit starts run.elf and loads init.elf.
- run starts init.
- init loads init.config and executes it.
- during that process, the initial programs are killed.
Order:
run.elf
init.elf
init.config
load.elf
drivers
emulations
programs
init.config is a script:
# load <name> = <filename> load a file into memory. Don't use this after killbootthreads.
load session = session.config
load driver_lcd = lcd.elf
load driver_buzzer = buzzer.elf
load driver_gpio = gpio.elf
load driver_audio = audio.elf
load driver_udc = udc.elf
load driver_nand = nand.elf
load emu_lcd = emu_display.elf
load emu_buzzer = emu_buzzer.elf
load emu_keyboard = emu_keyboard.elf
load emu_audio = emu_audio.elf
load emu_udc = emu_udc.elf
# killbootthreads destroy bootinit, bootfs and bootstore.
killbootthreads
# receive <cap> = <name> (<type> [, <index>]) prepare to accept a capability from a named program.
receive display = driver_lcd (display)
receive display_bright = driver_lcd (setting)
receive buzzer = driver_buzzer (buzzer)
receive keyboard = driver_gpio (keyboard, 0)
receive sysreq = driver_gpio (keyboard, 1)
receive audio = driver_audio (audio)
receive udc = driver_udc (udc)
receive nand = driver_nand (wstring)
# driver <name> run a previously loaded program priviledged.
driver driver_lcd
driver driver_buzzer
driver driver_gpio
driver driver_audio
driver driver_udc
driver driver_nand
# wait wait until all expected capabilities are received.
wait
# sysreq <cap> use a capability as the system request keyboard.
sysreq sysreq
# give <name> (<type> [, <index>]) = <cap> give this capability to this program when it requests it.
give emu_display (display) = display
give emu_display_bright (setting) = display_bright
give emu_buzzer (buzzer) = buzzer
give emu_keyboard (keyboard, 0) = keyboard
give emu_audio (audio) = audio
give emu_udc (udc) = udc
# run <name> run a previously loaded program (normally).
run emu_lcd
run emu_buzzer
run emu_keyboard
run emu_audio
run emu_udc
# include <name> include a loaded file as another config file.
include session
# loop sit and do nothing (respond to system request).
loop

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% Iris: micro-kernel for a capability-based operating system.
% cross-compiler.tex: Cross-compiler building instructions.
% Copyright 2009 Bas Wijnen <wijnen@debian.org>
%
% This program is free software: you can redistribute it and/or modify
% it under the terms of the GNU General Public License as published by
% the Free Software Foundation, either version 3 of the License, or
% (at your option) any later version.
%
% This program is distributed in the hope that it will be useful,
% but WITHOUT ANY WARRANTY; without even the implied warranty of
% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
% GNU General Public License for more details.
%
% You should have received a copy of the GNU General Public License
% along with this program. If not, see <http://www.gnu.org/licenses/>.
\documentclass{shevek}
\begin{document}
\title{Setting up a cross-compiler}
\author{Bas Wijnen}
\date{\today}
\maketitle
\begin{abstract}
This report details how I have set up a cross-compiler. Since it was not
trivial, I think it may be useful for others. After reading this, you should
be able to set up a cross-compiler yourself. It is assumed that the host computer, where the compiler should be running, is a Debian machine.
\end{abstract}
\tableofcontents
\section{Introduction}
A cross-compiler is a compiler which builds code that should be run on a different platform. This can be useful for building code for embedded devices which are incapable of running a compiler themselves, or where it is not practical to do so. If you are reading this, you probably need one. I'm sure you know why you do. Possibly you have also found out that it is not trivial to set it up. This is a step by step report of how I set up a cross-compiler for mipsel. All problems I encountered (and solved) are explained.
A cross-compiler needs cross-binutils and some system libraries. I shall first describe how to install these.
\section{Binutils}
To create a cross-compiler, cross-binutils are needed. They must be built from
source. I did \verb+apt-get source binutils+ to get the sources, then I cd'd into the source directory and did
\verb+TARGET=mipsel-linux-gnu fakeroot debian/rules binary-cross+ to build and
in the original directory \verb+dpkg -i *.deb+ (as root) to install them.
\section{System libraries}
libc6-dev and some other libraries must be installed in cross versions.
\textit{dpkg-cross} is used to build and install them. However, that doesn't
resolve dependencies, and can't download files from a mirror. So that's a
problem. Furthermore, once the compiler is working, other cross-libraries may
be required for the actual cross-building. Then again, the dependencies must
be resolved. It is not practical to do that by hand.
For this purpose, I wrote a script which resolves dependencies of a packages,
filters them to remove the unneeded ones, downloads them and installs them with
dpkg-cross. This is very hackish: it uses human-readable output of programs
like apt-cache to do its work. This output can change its format, I suppose.
But so far I didn't find any other way, so it'll have to do. At least it works
for me. Note that the user running the script must be allowed to run
dpkg-cross as root using sudo. This is achieved (for anyone, not just that
user) by adding to /etc/sudoers \verb+ALL ALL=NOPASSWD:/usr/bin/dpkg-cross+.
In /etc/dpkg-cross/cross-compile, you will need to add your gcc version to the
keepdeps line, in my case \verb+gcc-4.2-base+. This didn't seem to be possible
with command line options (so the comment above that block probably refers only
to the removedeps line).
When this is done, cross-libraries can be installed using the script. I needed
\verb+./cross-install libc6-dev libc6-dev-mips64 libc6-dev-mipsn32+. This
results in packages with those names and \verb+-mipsel-cross+ appended.
\section{Gcc}
For gcc, I did \verb+apt-get source gcc-4.2+ (4.3 didn't work), followed by
\verb+export GCC_TARGET=mipsel+ and \verb+export DEB_CROSS_INDEPENDENT=yes+.
Then in the source directory \verb+debian/rules control+, and finally
\verb+dpkg-buildpackage -uc -us -b -rfakeroot+ and of course
\verb+dpkg --install *.deb+ in the original directory. This failed for
gobjc++-4.2, which I didn't need anyway, so I removed it again.
That results in a cross compiler which can be called using
\verb+mipsel-linux-gnu-gcc+.
\section{Conclusion}
Setting up a cross-compiler is much harder than it should be. Especially
sorting out the dependencies and downloading libraries is very hard. It would
be good if this would be made easier. My cross-install script does this, but
in a fragile and hackish way. However, it does result in a usable
cross-building environment, where new libraries for cross-building can be
easily installed.
\end{document}

388
report/kernel.tex
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% Iris: micro-kernel for a capability-based operating system.
% kernel.tex: Description of Iris.
% Copyright 2009 Bas Wijnen <wijnen@debian.org>
%
% This program is free software: you can redistribute it and/or modify
% it under the terms of the GNU General Public License as published by
% the Free Software Foundation, either version 3 of the License, or
% (at your option) any later version.
%
% This program is distributed in the hope that it will be useful,
% but WITHOUT ANY WARRANTY; without even the implied warranty of
% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
% GNU General Public License for more details.
%
% You should have received a copy of the GNU General Public License
% along with this program. If not, see <http://www.gnu.org/licenses/>.
\documentclass{shevek}
\begin{document}
\title{Overview of Iris}
\author{Bas Wijnen}
\date{\today}
\maketitle
\begin{abstract}
This document briefly describes the inner workings of my kernel, Iris,
including the reasons for the choices that were made. It is meant to be
understandable (with effort) for people who know nothing of operating systems.
On the other hand, it should also be readable for people who know about
computer architecture, but want to know about this kernel. It is probably
better suited for the latter category.
\end{abstract}
\tableofcontents
\section{Operating systems}
This section describes what the purpose of an operating system is, and defines
what I call an ``operating system''\footnote{Different people use very
different definitions, so this is not as trivial as it sounds.}. It also goes
into some detail about microkernels and capabilities. If you already know, you
can safely skip this section. It contains no information about Iris.
\subsection{The goal of an operating system}
In the 1980s, a computer could only run one program at a time. When the
program had finished, the next one could be started. This follows the
processor itself: it runs a program, from the beginning until the end, and
can't run more than one program simultaneously\footnote{Multi-core processors
technically can run multiple programs simultaneously, but I'm not talking about
those here.}. In those days, an \textit{operating system} was the program that
allowed other programs to be started. The best known operating systems were
called \textit{Disk operating system}, or \textit{DOS} (of which there were
several).
At some point, there was a need for programs that would ``help'' other programs
in some way. For example, they could provide a calculator which would pop up
when the user pressed a certain key combination. Such programs were called
\textit{terminate and stay resident} programs, or TSRs. This name came from
the fact that they terminated, in the sense that they would allow the next
program to be run, but they would stay resident and do their job in the
background.
At some point, people wanted to de \textit{multitasking}. That is, multiple
``real'' programs should run concurrently, not just some helpers. The easiest
way to implement this is with \textit{cooperative multitasking}. Every program
returns control to the system every now and then. The system switches between
all the running programs. The result is that every program runs for a short
time, several times per second. For the user, this looks like the programs are
all running simultaneously, while in reality it is similar to a chess master
playing simultaneously on many boards: he really plays on one board at a time,
but switches a lot. On such a system, the \textit{kernel} is the program that
chooses which program to run next. The \textit{operating system} is the kernel
plus some support programs which allow the user to control the system.
On a system where multiple programs all think they ``own'' the computer, there
is another problem: if more than one program tries to access the same device,
it is very likely that at least one of them, and probably both, will fail. For
this reason, \textit{device drivers} on a multitasking system must not only
allow the device to be controlled, but they must also make sure that concurrent
access doesn't fail. The simplest way to achieve this is simply to disallow
it (let all operations fail that don't come from the first program using the
driver). A better way, if the device can handle it, is to somehow make sure
that both work.
There is one problem with cooperative multitasking: when one program crashes,
or for some other reason doesn't return control to the system, the other
programs stop running as well. The solution to this is \textit{preemptive
multitasking}. This means that every program is interrupted every now and
then, without asking for it, and the system switches to a different program.
This makes the kernel slightly more complex, because it must take care to store
every aspect of the running programs. After all, the program doesn't expect to
be interrupted, so it can't expect its state to change either. This shouldn't
be a problem though. It's just something to remember when writing the kernel.
Concluding, every modern desktop kernel uses preemptive multitasking. This
requires a timer interrupt. The operating system consists of this kernel, plus
the support programs that allow the user to control the system.
\subsection{Microkernel}
Most modern kernels are so-called \textit{monolithic} kernels: they include
most of the operating system. In particular, they include the device drivers.
This is useful, because the device drivers need special attention anyway, and
they are very kernel-specific. Modern processors allow the kernel to protect
access to the hardware, so that programs can't interfere with each other. A
device driver which doesn't properly ask the kernel will simply not be allowed
to control the device.
However, adding device drivers and everything that comes with them
(filesystems, for example) to the kernel makes it a very large program.
Furthermore, it makes it an ever-changing program: as new devices are built,
new drivers must be added. Such a program can never become stable and
bug-free.
Conceptually much nicer is the microkernel. It includes the minimum that is
needed for a kernel, and nothing more. It does include task switching and some
mehtod for tasks to communicate with each other. It also ``handles'' hardware
interrupts, but all it really does is passing them to the device driver, which
is mostly a normal program. Some microkernels don't do memory manangement
(deciding which programs get how much and which memory), while others do.
The drawback of a microkernel is that it requires much more communication
between tasks. Where a monolithic kernel can serve a driver request from a
task directly, a microkernel must pass it to a device driver. Usually there
will be an answer, which must be passed back to the task. This means more task
switches. This doesn't need to be a big problem, if task switching is
optimized: because of the simpler structure of the microkernel, it can be much
faster at this than a monolithic kernel. And even if the end result is
slightly slower, in my opinion the stability is still enough reason to prefer a
microkernel over a monolitic one.
Summarizing, a microkernel needs to do task switching and inter-process
communication. Because mapping memory into an address space is closely related
to task switching, it is possible to include memory management as well. The
kernel must accept hardware interrupts, but doesn't handle them (except the
timer interrupt).
\subsection{Capabilities}
Above I explained that the kernel must allow processes to communicate. Many
systems allow communication through the filesystem: one process writes to a
file, and an other process reads from it. This implies that any process can
communicate with any other process, if they only have a place to write in the
filesystem, where the other can read.
This is a problem because of security. If a process cannot communicate with
any part of the system, except the parts that it really needs to perform its
operation, it cannot leak or damage the other parts of the system either. The
reason that this is relevant is not that users will run programs that try to
ruin their system (although this may happen as well), but that programs may
break and damage random parts of the system, or be taken over by
crackers\footnote{Crackers are better known by the public as ``hackers''.
However, I use this word to describe people who like to play with software (or
sometimes also with other things). Therefore the malicious people who use
hacking skills for evil need a different name.}. If the broken or malicious
process has fewer rights, it will also do less damage to the system.
This leads to the goal of giving each process as little rights as possible.
For this, it is best to have rights in a very fine-grained way. Every
operation of a driver (be it a hardware device driver, or just a shared program
such as a file system) should have its own key, which can be given out without
giving keys to the entire driver (or even multiple drivers). Such a key is
called a capability. For example, a capability can allow the holder to access
a single file, or to use one specific network connection, or to see what keys
are typed by the user.
Some operations are performed directly on the kernel itself. For those, the
kernel can provide its own capabilities. Processes can create their own
objects which can receive capability calls, and capabilities for those can be
generated by them. Processes can copy capabilities to other processes, if they
have a channel to send them (using an existing capability). This way, any
operation of the process with the external world goes through a capability, and
only one system call is needed: \textit{invoke}.
This has a very nice side-effect, which is that it becomes very easy to tap
communication of a task you control. This means that a user can redirect
certain requests from programs which don't do exactly what is desired to do
nicer things. For example, a program can be prevented from opening pop-up
windows. In other words, it puts control of the computer from the programmer
into the hands of the user (as far as allowed by the system administrator).
This is a very good thing.
\section{Communication}
This section shortly describes how communication between threads is performed
by Iris. Below are more details about the kernel structures, this section just
explains which steps are taken.
Iris doesn't hold any state about the communication, other than the state that
it holds for threads on request of the threads (in the memory paid for by the
threads). For Iris, there is no such thing as a \textit{conversation}. There
are messages. When there is a conversation, Iris just sees several messages
going both ways. For Iris these are not connected\footnote{This is not
entirely true; Iris has call capabilities as an optimization feature. They do
implement some conversation aspects. But they are only an optimization: Iris
doesn't require them to be used.}.
So understanding communication between threads boils down to understanding the
transfer of a single message. A message is short: four 32-bit words of data,
plus four capabilities. Besides that, a 64-bit protected value is sent. This
value is set by the creator of the capability, usually the server, and cannot
be changed by the invoker.
Sending a message between threads is mostly about a Receiver object. The
server has a Receiver, for which it creates a capability (with the mentioned
protected data). If a client wants to contact the server, it must get this
capability.
The client then invokes the capability with four data words and four
capabilities (possibly set to 0). The message is queued by the receiver. The
capabilities are stored into a Caps object.
When the server is ready for it, it queries the receiver for new messages. It
then gets the protected data, the four data words and copies of the
capabilities. The ones in the receiver's Caps are invalidated and can be
reused after that. Note that it does not get a capability of the sender,
unless the sender sends it. There is no way for the server to know who is
sending the message, only which capability was used (through the protected
data).
\section{Kernel objects}
This section describes all kernel objects of Iris, and the operations that can
be performed on them. One operation is possible on any kernel object (except a
message and reply and call Capabilities). This operation is \textit{degrade}.
It creates a copy of the capability with some rights removed. This can be
useful when giving away a capability.
\subsection{Memory}
A Memory object is a container for storing things. All objects live inside a
Memory object. A Memory object can contain other Memory objects, Capabilities,
Receivers, Threads, Pages and Cappages.
A Memory object is also an address space. Pages can be mapped (and unmapped).
Any Thread in a Memory object uses this address space while it is running.
Every Memory object has a limit. When this limit is reached, no more Pages can
be allocated for it (including Pages which it uses to store other objects).
Using a new Page in a Memory object implies using it in all ancestor Memory
objects. This means that setting a limit which is higher than the parent's
limit means that the parent's limit applies anyway.
Operations on Memory objects:
\begin{itemize}
\item Create a new item of type Receiver, Memory, Thread, Page, or Cappage.
\item Destroy an item of any type, which is owned by the Memory.
\item List items owned by the Memory, Pages mapped in it, and messages in owned
Receiver's queues.
\item Map a Page at an address.
\item Get the Page which is mapped at a certain address.
\item Get and set the limit, which is checked when allocating pages for this
Memory or any sub-structure.
\item Drop a capability. This can only be done by Threads owned by the Memory,
because only they can present capabilities owned by it.\footnote{Iris checks if
presented capabilities are owned by the Thread's Memory. If they aren't, no
capability is passed instead. The destroy operation destroys an object that a
capability points to. Drop destroys the capability itself. If a Thread from
an other Memory would try to drop a capability, Iris would refuse to send it in
the message, or it would not be dropped because it would be owned by a
different Memory.}
\end{itemize}
\subsection{Receiver}
A receiver object is used for inter-process communication. Capabilities can be
created from it. When those are invoked, the receiver can be used to retrieve
the message.
Operations on Receiver objects:
\begin{itemize}
\item Set the owner. This is the Thread that messages will be sent to when
they arrive. Messages are stored in the receiver until the owner is ready to
accept them. If it is waiting while the message arrives, it is immediately
delivered.
\item Create a capability. The new capability should be given to Threads who
need to send a message to the receiver.
\item Create a call capability. This is an optimization. Because
\textit{calls} happen a lot, where a capability is created, sent in a message,
then a reply is sent over this new capability, and then it is dropped. This
can be done using a call capability. The call capability is invoked instead of
the target, and the target is specified where the reply capability should be.
The message is sent to the call capability (which is handled by the Receiver in
the kernel). It creates a new reply capability and sends the message to the
target with it. When the reply capability is invoked, the message is sent to
the owner, and the capability is dropped. This approach reduces the number of
kernel calls from four (create, call, reply, drop) to two (call, reply).
\end{itemize}
\subsection{Thread}
Thread objects hold the information about the current state of a thread. This
state is used to continue running the thread. The address space is used to map
the memory for the Thread. Different Threads in the same address space have
the same memory mapping. All Threads in one address space (often there is only
one) together are called a process.
Because all threads have a capability to their own Thread object (for claiming
Receivers), this is also used to make some calls which don't actually need an
object. The reason that these are not operations on some fake object which
every process implicitly owns, is that for debugging it may be useful to see
every action of a process. In that case, all its capabilities must be pointing
to the watcher, which will send them through to the actual target (or not).
With such an implicit capability, it would be impossible to intercept these
calls.
Operations on Thread objects:
\begin{itemize}
\item Get information about the thread. Details of this are
architecture-specific. Standard ways are defined for getting and setting some
flags (whether the process is running or waiting for a message, setting these
flags is a way to control this for other Threads), the program counter and the
stack pointer. This call is also used to get the contents of processor
registers and possibly other information which is different per Thread.
\item Let Iris schedule the next process. This is not thread-specific.
\item Get the top Memory object. This is not thread-specific. Most Threads
are not allowed to perform this operation. It is given to the initial Threads.
They can pass it on to Threads that need it (if any).
\item In the same category, register a Receiver for an interrupt. Upon
registration, the interrupt is enabled. When the interrupt arrives, the
registered Receiver gets a message from Iris and the interrupt is disabled
again. After the Thread has handled the interrupt, it must reregister it in
order to enable it again.
\item Allocate a range of contiguous physical memory. This is only relevant
for device drivers whose device will directly access the storage, such as the
display driver. The result of this call is that the memory is counted as used
by the Thread, and it is reserved, but it is not returned. Instead, the
address of physical memory is returned, and the pages need to be retrieved with
the next operation. This capability is not present in normally created
threads.
\item Allocate a page of physical memory. This is used in combination with the
previous operation to reserve a block of physical memory, and by device drivers
to map I/O memory into their address space. There is a flag indicating whether
this memory should be freed (ranges) or not (I/O). Users of this operation are
trusted to handle it properly; no checks are done to ensure that no kernel
memory is leaked, or that the allocated memory isn't used by other threads or
the kernel. Of course, this capability is not present in normally created
threads.
\item Get the physical address of a page. Only device drivers need to know the
physical address of their pages, so this operation is not available on normal
threads.
\item And similarly, allow these priviledged operations (or some of them) in an
other thread. This is a property of the caller, because the target thread
normally doesn't have the permission to do this (otherwise the call would not
be needed). The result of this operation is a new Thread capability with all
specified rights set. Normally this is inserted in a priviledged process's
address space during setup, before it is run (instead of the capability which
is obtained during Thread creation).
\end{itemize}
\subsection{Page and Cappage}
A Page can be used to store user data. It can be mapped into an address space
(a Memory object). Threads can then use the data directly. A Cappage is very
similar, in that it is owned by the user. However, the user cannot see its
contents directly. It contains a frame with Capabilities. They can be invoked
like other owned capabilities. The main feature of a Cappage, however, is that
they can be shared. It is a fast way to copy many capabilities to a different
address space. Capabilities in a Cappage are not directly owned by the Memory,
and thus cannot be dropped.
Operations on Page and Cappage objects:
\begin{itemize}
\item Copy or move the frame to a different Page, which is usually in a
different Memory. This way, large amounts of data can be copied between
address spaces without needing to really copy it.
\item Set or get flags, which contain information on whether the page is
shared, is writable, has a frame allocated, and is paying for the frame. Not
all flags can be set in all cases.
\item Cappages can also set a capability in the frame (pointed to with an index).
\end{itemize}
\subsection{Capability}
A capability object can be invoked to send a message to a receiver or to Iris
itself. The owner cannot see from the capability where it points. This is
important, because the user must be able to substitute the capability for a
different one, without the program noticing. In some cases, it is needed to
say things about capabilities. For example, a Memory can list the Capabilities
owned by it. In such a case, the list consists of Capabilities which point to
other Capabilities. These capabilities can also be used to destroy the target
capability (using an operation on the owning Memory object), for example.
Operations or capability objects:
\begin{itemize}
\item Get a copy of the capability.
\end{itemize}
\section{Interface classes}
Around Iris is a system of some programs to create the operating system. These
include the device drivers. While Iris itself needs no specific interfaces
from them, some interface classes are defined, which are used by the default
environment. By defining classes, it is possible to let a program use any
device of that type without needing changes to its code.
These definitions are in the source. A copy of the information here would only
lead to it getting outdated.
\end{document}

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% Iris: micro-kernel for a capability-based operating system.
% making-of.tex: Description of the process of writing Iris.
% Copyright 2009 Bas Wijnen <wijnen@debian.org>
%
% This program is free software: you can redistribute it and/or modify
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\documentclass{shevek}
\begin{document}
\title{Writing a kernel from scratch}
\author{Bas Wijnen}
\date{\today}
\maketitle
\begin{abstract}
This is a report of the process of writing a kernel (Iris) from scratch for
the cheap (€150) Trendtac laptop. In a following report I shall write about
the operating system on top of it. This document is written while writing the
system, so that no steps are forgotten. Choices are explained and problems
(and their solutions) are shown. After reading this, you should have a
thorough understanding of Iris, and (with significant effort) be able to write
a similar kernel yourself. This document assumes a working Debian system with
root access (for installing packages), and some knowledge about computer
architectures. (If you lack that knowledge, you can try to read it anyway and
check other sources when you see something new.)
\end{abstract}
\tableofcontents
\section{Hardware details}
The first step in the process of writing an operating system is finding out
what the system is you're going to program for. While most of the work is
supposed to be platform--independant, some parts, especially in the beginning,
will depend very much on the actual hardware. So I searched the net and found:
\begin{itemize}
\item There's a \textbf{Jz4730} chip inside, which implements most
functionality. It has a mips core, an OHCI USB host controller (so no USB2),
an AC97 audio device, a TFT display controller, an SD card reader, a network
device, and lots of general purpose I/O pins, which are used for the LEDs and
the keyboard. There are also two PWM outputs, one of which seems to be used
with the display. It also has some other features, such as a digital camera
controller, which are not used in the design.
\item There's a separate 4-port USB hub inside.
\item There's a serial port which is accessible with a tiny connector inside
the battery compartiment. It uses TTL signals, so to use it with a PC serial
port, the signals must be converted with a MAX232. That is normal for these
boards, so I already have one handy. The main problem in this case is that the
connector is an unusual one, so it may take some time until I can actually
connect things to the serial port.
\end{itemize}
First problem is how to write code which can be booted. This seems easy: put a
file named \textbf{uimage} on the first partition on an SD card, which must be
formatted FAT or ext3, and hold down Fn, left shift and left control while
booting. The partition must also not be larger than 32 MB.
The boot program is u-boot, which has good documentation on the web. Also,
there is a Debian package named uboot-mkimage, which has the mkimage executable
to create images that can be booted using u-boot. uimage should be in this
format.
To understand at least something of addresses, it's important to understand the
memory model of the mips architecture:
\begin{itemize}
\item usermode code will never reference anything in the upper half of the
memory (above 0x80000000). If it does, it receives a segmentation fault.
\item access in the lower half is paged and can be cached. This is called
kuseg when used from kernel code. It will access the same pages as non-kernel
code finds there.
\item the upper half is divided in 3 segments.
\item kseg0 runs from 0x80000000 to 0xa0000000. Access to this memory will
access physical memory from 0x00000000 to 0x20000000. It is cached, but not
mapped (meaning it accesses physical, not virtual, memory)
\item kseg1 runs from 0xa0000000 to 0xc0000000. It is identical to kseg0,
except that is is not cached.
\item kseg2 runs from 0xc0000000 to the top. It is mapped like user memory,
differently for each process, and can be cached. It is intended for
per-address space kernel structures. I shall not use it in Iris.\footnote{I
thought I wouldn't use kseg2. However, I needed to use it for kernel entry
code, as you can read below.}
\end{itemize}
U-boot has some standard commands. It can load the image from the SD card at
0x80600000. Even though the Linux image seems to use a different address, I'll
go with this one for now.
\section{Cross-compiler}
Next thing to do is build a cross-compiler so it is possible to try out some
things. This shouldn't need to be very complex, but it is. I wrote a separate
document about how to do this. Please read that if you don't have a working
cross-compiler, or if you would like to install libraries for cross-building
more easily.
\section{Choosing a language to write in}
Having a cross-compiler, the next thing to do is choose a language. I prefer
to use C++ for most things. I have used C for a previous kernel, though,
because it is more low-level. This time, I decided to try C++. But since I'm
not linking any libraries, I need to avoid things like new and delete. For
performance reasons I also don't use exceptions. They might need library
support as well. So what I use C++ for is classes with member functions, and
default function arguments. I'm not even using these all the time, and the
whole thing is very much like C anyway.
Except for one change I made: I'm using a \textit{pythonic preprocessor} I
wrote. It changes python-style indented code into something a C compiler
accepts. It shouldn't be too hard to understand if you see the kernel source.
Arguments to flow control instructions (if, while, for) do not need
parenthesis, but instead have a colon at the end of the line. After a colon at
the end of a line follows a possibly empty indented block, which is put in
brackets. Indenting a line with respect to the previous one without a colon
will not do anything: it makes it a continuation. Any line which is not empty
or otherwise special gets a semicolon at the end, so you don't need to type
those. When using both spaces and tabs (which I don't recommend), set the tab
width to 8 spaces.
\section{Making things run}
For loading a program, it must be a binary executable with a header. The
header is inserted by mkimage. It needs a load address and an entry point.
Initially at least, the load address is 0x80600000. The entry point must be
computed from the executable. The easiest way to do this is by making sure
that it is the first byte in the executable. The file can then be linked as
binary, so without any headers. This is done by giving the
\verb+--oformat binary+ switch to ld. I think the image is loaded without the
header, so that can be completely ignored while building. However, it might
include it. In that case, the entry point should be 0x40 higher, because
that's the size of the header.
\section{The first version of the kernel}
This sounds better than it is. The first version will be able to boot, and
somehow show that it did that. Not too impressive at all, and certainly not
usable. It is meant to find out if everything I wrote above actually works.
For this kernel I need several things: a program which can boot, and a way to
tell the user. As the way to tell the user, I decided to use the caps-lock
LED. The display is quite complex to program, I suppose, so I won't even try
at this stage. The LED should be easy. Especially because Linux can use it
too. I copied the code from the Linux kernel patch that seemed to be about the
LED, and that gave me the macros \verb+__gpio_as_output+, \verb+__gpio_set_pin+
and \verb+__gpio_clear_pin+. And of course there's \verb+CAPSLOCKLED_IO+,
which is the pin to set or clear.
I used these macros in a function I called \verb+kernel_entry+. In an endless
loop, it switches the LED on 1000000 times, then off 1000000 times. If the
time required to set the led is in the order of microseconds, the LED should be
blinking in the order of seconds. I tried with 1000 first, but that left the
LED on seemingly permanently, so it was appearantly way too fast.
This is the code I want to run, but it isn't quite ready for that yet. A C
function needs to have a stack when it is called. It is possible that u-boot
provides one, but it may also not do that. To be sure, it's best to use some
assembly as the real entry point, which sets up the stack and calls the
function.
The symbol that ld will use as its entry point must be called \verb+__start+
(on some other architectures with just one underscore). So I created a simple
assembly file which defines some stack space and does the setting up. It also
sets \$gp to the so-called \textit{global offset table}, and clears the .bss
section. This is needed to make compiler-generated code run properly.
Now how to build the image file? This is a problem. The ELF format allows
paged memory, which means that simply loading the file may not put everything
at its proper address. ld has an option for this, \verb+--omagic+. This is
meant for the a.out format, which isn't supported by mipsel binutils, but that
doesn't matter. The result is still that the .text section (with the
executable code) is first in the file, immediately followed by the .data
section. So that means that loading the file into memory at the right address
results in all parts of the file in the proper place. Adding
\verb+-Ttext 0x80600000+ makes everything right. However, the result is still
an ELF file. So I use objcopy with \verb+-Obinary+ to create a binary file
from it. At this point, I also extract the start address (the location of
\verb+__start+) from the ELF file, and use that for building uimage. That
way it is no longer needed that \_\_start is at the first byte of the file.
Booting from the SD card is as easy as it seemed, except that I first tried an
mmc card (which fits in the same slot, and usually works when SD is accepted)
and that didn't work. So you really need an SD card.
\section{Context switching}
One very central thing in the kernel is context switching. That is, we need to
know how the registers and the memory are organized when a user program is
running. In order to understand that, we must know how paging is done. I
already found that it is done by coprocessor 0, so now I need to find out how
that works.
On the net I found the \textit{MIPS32 architecture for developers}, version 3
of which is sub-titled \textit{the MIPS32 priviledged resource architecture}.
It explains everything there is to know about things which are not accessible
from normal programs. In other words, it is exactly the right book for
programming a kernel or device driver using this processor. How nice.
It explains that memory accesses to the lower 2GB are (almost always) mapped
through a TLB (translation lookaside buffer). This is an array of some records
where virtual to physical address mappings are stored. In case of a TLB-miss
(the virtual address cannot be found in the table), an exception is generated
and Iris must insert the mapping into the TLB.
This is very flexible, because I get to decide how I write the kernel. I shall
use something similar to the hardware implementation of the IBM PC: a page
directory which contains links to page tables, with each page table filled with
pointers to page information. It is useful to have a direct mapping from
virtual address to kernel data as well. There are several ways how this can be
achieved. The two simplest ones each have their own drawback: making a shadow
page directory with shadow page tables with links to the kernel structures
instead of the pages wastes some memory. Using only the shadow, and doing a
lookup of the physical address in the kernel structure (where it must be stored
anyway) wastes some cpu time during the lookup. At this moment I do not know
what is more expensive. I'll initially go for the cpu time wasting approach.
\section{Kernel entry}
Now that I have an idea of how a process looks in memory, I need to implement
kernel entry and exit. A process is preempted or makes a request, then Iris
responds, and then a process (possibly the same) is started again.
The main problem of kernel entry is to save all registers in the kernel
structure which is associated with the thread. In case of the MIPS processor,
there is a simple solution: there are two registers, k0 and k1, which cannot be
used by the thread. So they can be set before starting the thread, and will
still have their values when the kernel is entered again.\footnote{This is not
true, see below.} By pointing one of them to the place to save the data, it
becomes easy to perform the save and restore.
As with the bootstrap process, this must be done in assembly. In this case
this is because the user stack must not be used, and a C function will use the
current stack. It will also mess up some registers before you can save them.
The next problem is how to get the interrupt code at its address. I'll try to
load the thing at address 0x80000000. It seems to work, which is good. Linux
probably has some reason to do things differently, but if this works, it is the
easiest way.
\section{Memory organization}
Now I've reached the point where I need to create some memory structures. To
do that, I first need to decide how to organize the memory. There's one very
simple rule in my system: everyone must pay for what they use. For memory,
this means that a process brings its own memory where Iris can write things
about it. Iris does not need her own allocation system, because she always
works for some process. If the process doesn't provide the memory, the
operation will fail.\footnote{There are some functions with \textit{alloc} in
their name. However, they allocate pieces of memory which is owned by the
calling process. Iris never allocates anything for herself, except during
boot.}
Memory will be organized hierarchically. It belongs to a container, which I
shall call \textit{Memory}. The entire Memory is the property of another
Memory, its parent. This is true for all but one, which is the top level
Memory. The top level Memory owns all memory in the system. Some of it
directly, most of it through other Memories.
Iris will have a list of unclaimed pages. For optimization, she actually
has two lists: one with pages containing only zeroes, and one with pages
containing junk. When idle, the junk pages can be filled with zeroes.
Because Iris starts at address 0, building up the list of pages is very
easy: starting from the first page above the top of the kernel, everything is
free space. Initially, all pages are added to the junk list.
\section{The idle task}
When there is nothing to do, an endless loop should be waiting for interrupts.
This loop is called the idle task. I use it also to exit bootstrapping, by
enabling interrupts after everything is set up as if we're running the idle
task, and then jumping to it.
There are two options for the idle task, again with their own drawbacks. The
idle task can run in kernel mode. This is easy, it doesn't need any paging
machinery then. However, this means that Iris must read-modify-write the
Status register of coprocessor 0, which contains the operating mode, on every
context switch. That's quite an expensive operation for such a critical path.
The other option is to run it in user mode. The drawback there is that it
needs a page directory and a page table. However, since the code is completely
trusted, it may be possible to sneak that in through some unused space between
two interrupt handlers. That means there's no fault when accessing some memory
owned by others (which is a security issue), but the idle task is so trivial
that it can be assumed to run without affecting them.
\section{Intermezzo: some problems}
Some problems came up while working. First, I found that the code sometimes
didn't work and sometimes it did. It seemed that it had problems when the
functions I called became more complex. Looking at the disassembly, it appears
that I didn't fully understand the calling convention used by the compiler.
Appearantly, it always needs to have register t9 set to the called function.
In all compiled code, functions are called as \verb+jalr $t9+. It took quite
some time to figure this out, but setting t9 to the called function in my
assembly code does indeed solve the problem.
I also found that every compiled function starts with setting up gp. This is
complete nonsense, since gp is not changed by any code (and it isn't restored
at the end of a function either). I'll report this as a but to the compiler.
Because it is done for every function, it means a significant performance hit
for any program.
The other problem is that the machine was still doing unexpected things.
Appearantly, u-boot enables interrupts and handles them. This is not very nice
when I'm busy setting up interrupt handlers. So before doing anything else, I
first switch off all interrupts by writing 0 to the Status register of CP0.
This also reminded me that I need to flush the cache, so that I can be sure
everything is correct. For that reason, I need to start at 0xa0000000, not
0x80000000, so that the startup code is not cached. It should be fine to load
Iris at 0x80000000, but jump in at the non-cached location anyway, if I
make sure the initial code, which clears the cache, can handle it. After that,
I jump to the cached region, and everything should be fine. However, at this
moment I first link Iris at the non-cached address, so I don't need to
worry about it.\footnote{Actually, it seems that the cache is working fine, and
I'm using the cached address. They are used for kernel entry in any case.}
Finally, I read in the books that k0 and k1 are in fact normal general purpose
registers. So while they are by convention used for kernel purposes, and
compilers will likely not touch them, Iris can't actually rely on them not
being changed by user code. So I'll need to use a different approach for
saving the processor state. The solution is trivial: use k1 as before, but
first load it from a fixed memory location. To be able to store k1 itself, a
page must be mapped in kseg3 (wired into the tlb), which can then be accessed
with a negative index to \$zero.
At this point, I was completely startled by crashes depending on seemingly
irrelevant changes. After a lot of investigation, I saw that I had forgotten
that mips jumps have a delay slot, which is executed after the jump, before the
first new instruction is executed. I was executing random instructions, which
lead to random behaviour.
\section{Back to the idle task}
With all this out of the way, I continued to implement the idle task. I hoped
to be able to never write to the Status register. However, this is not
possible. The idle task must be in user mode, and it must call wait. That
means it needs the coprocessor 0 usable bit set. This bit may not be set for
normal processes, however, or they would be able to change the tlb and all
protection would be lost. However, writing to the Status register is not a
problem. First of all, it is only needed during a task switch, and they aren't
as frequent as context switches (every entry to the kernel is a context switch,
only when a different task is entered from the kernel than exited to the kernel
is it a task switch). Furthermore, and more importantly, coprocessor 0 is
intgrated into the cpu, and writing to it is actually a very fast operation and
not something to be avoided at all.
So to switch to user mode, I set up the Status register so that it looks like
it's handling an exception, set EPC to the address of the idle task, and use
eret to ``return'' to it.
\section{Timer interrupts}
This worked well. Now I expected to get a timer interrupt soon after jumping
to the idle task. After all, I have set up the compare register, the timer
should be running and I enabled the interrupts. However, nothing happened. I
looked at the contents of the count register, and found that it was 0. This
means that it is not actually counting at all.\footnote{I also checked the
random register, which didn't seem to change either. This is a huge
performance problem, but it is easily solved by changing the random register
manually.} Looking at the Linux sources, they don't use this timer either, but
instead use the cpu-external (but integrated in the chip) timer. The
documentation says that they have a different reason for this than a
non-functional cpu timer. Still, it means it can be used as an alternative.
Having a timer is important for preemptive multitasking: a process needs to be
interrupted in order to be preempted, so there needs to be a periodic interrupt
source.
During testing it is not critical to have a timer interrupt. Without it, the
system can still do cooperative multitasking, and all other aspects of the
system can be tested. So I decided to leave the timer interrupts until I'm
going to write the drivers for the rest of the hardware as well.
\section{Invoke}
So now I need to accept calls from programs and handle them. For this, I need
to decide what such a call looks like. It will need to send a capability to
invoke, and a number of capabilities and numbers as arguments. I chose to send
four capabilities (so five in total) and also four numbers. The way to send
these is by setting registers before making a system call. Similarly, when
Iris returns a message, she sets the registers before returing to the program.
I wrote one file with assembly for receiving interrupts and exceptions
(including system calls) and one file with functions called from this assembly
to do most of the work. For syscall, I call an arch-specific\footnote{I split
off all arch-specific parts into a limited number of files. While I am
currently writing Iris only for the Trendtac, I'm trying to make it easy to
port her to other machines later.} invoke function, which reads the message,
puts it in variables, and calls the real invoke function.
The real invoke function analyzes the called capability: if it is in page 0
(which is used by the interrupt handlers, and cannot hold real capabilities),
it must be a kernel-implemented object. If not, it is a pointer to a Receiver.
Then kernel object calls are handled, and messages to receivers are sent. When
all is done, control is returned to the current process, which may or may not
be the calling process. If it isn't, the processor state is initialized for
the new process by setting the coprocessor 0 usable bit in the Status register
and the asid bits in the EntryHi register of CP0.
\section{Paging}
While implementing user programs, I needed to think about paging as well. When
a TLB miss occurs, the processor must have a fast way to reload it. For this,
page tables are needed. On Intel processors, these need to be in the format
that Intel considered useful. On a mips processor, the programmer can choose
whatever they want. The Intel format is a page containing the
\textit{directory}, 1024 pointers to other pages. Each of those pages contains
1024 pointers to the actual page. That way, 10 bits of the virtual address
come from the directory, 10 bits from the page table, and 12 from the offset
within the page, leading to a total of 32 bits of virtual memory addressing.
On mips, we need 31 bits, because addresses with the upper bit set will always
result in an address error. So using the same format would waste half of the
page directory. However, it is often useful to have address to mapped page
information as well. For this, a shadow page table structure would be needed.
It seems logical to use the upper half of the directory page for the shadow
directory. However, I chose a different approach: I used the directory for
bits 21 to 30 (as opposed to 22 to 31). Since there are still 12 bit
addressable pages, this leaves 9 bits for the page tables. I split every page
table in two, with the data for EntryLo registers in the lower half, and a
pointer to page information in the upper half of the page. This way, my page
tables are smaller, and I waste less space for mostly empty page tables.
To make a TLB refill as fast as possible, I implemented it directly in the
assembly handler. First, I check if k0 and k1 are both zero. If not, I use
the slow handler. If they are, I can use them as temporaries, and simply set
them to zero before returning. Then I read the current directory (which I save
during a task switch), get the proper entry from it, get the page table from
there, get the proper entry from that as well, and put that in the TLB. Having
done that, I reset k0 and k1, and return. No other registers are changed, so
they need not be saved either. If anything unexpected happens (there is no
page table or no page entry at the faulting address), the slow handler is
called, which will fail as well, but it will handle the failure. This is
slightly slower than handling the failure directly, but speed is no issue in
case of such a failure.
While implementing this, I have been searching for a problem for some time. In
the end, I found that the value in the EntryLo registers does not have the bits
at their normal locations, but 6 bits back. I was mapping the wrong page in,
and thus got invalid data when it was being used.
\section{Sharing}
The next big issue is sharing memory. In order to have efficient
communication, it is important to use shared memory. The question is how to
implement it. A Page can be mapped to memory in the address space that owns
it. It can be mapped to multiple locations in that address space. However I
may remove this feature for performance reasons. It doesn't happen much
anyway, and it is always possible to map the same frame (a page in physical
memory) to multiple virtual addresses by creating an multiple Pages.
For sharing, a frame must also be mappable in a different address space. In
that case, an operation must be used which copies or moves the frame from one
Page to another. There is a problem with rights, though: if there is an
operation which allows a frame to be filled into a Page, then the rights of
capabilities to that Page may not be appropriate for the frame. For example,
if I have a frame which I am not allowed to write, and a frame which I am
allowed to write, I should not be able to write to the first frame by
transferring it to the second Page. So some frame rights must be stored in the
Page, and they must be updated during copy and move frame operations.
Move frame is only an optimization. It allows the receiver to request a
personal copy of the data without actually copying anything. The result for
the sender is a Page without a frame. Any mappings it has are remembered, but
until a new frame is requested, no frame will be mapped at the address. A Page
is also able to \textit{forget} its frame, thereby freeing some of its memory
quota (if it stops paying for it as well; a payed-for frame costs quota, and is
guaranteed to be allocatable at any time).
Another optimization is to specify a minimum number of bytes for a page move.
If the page needs to be copied, this reduces the time needed to complete that
operation. The rest of the page should not contain secret data: it is possible
that the entire page is copied, for example if it doesn't need to be copied,
but can be reused.
\section{Copy on write}
Another nice optimization is \textit{copy on write}: a page is shared
read-only, and when a page-fault happens, the kernel will copy the contents, so
that the other owner(s) don't see the changes. For the moment, I don't
implemnt this. I'm not sure if I want it in Iris at all. It can well be
implemented using an exception handler in user space, and may not be used
enough to spend kernel space on. But I can change my mind on that later.
\section{Memory listing}
The last thing to do for now is allowing a memory to be listed. That is,
having a suitably priviledged capability to a Memory should allow a program to
see what's in it. In particular, what objects it holds, and where pages are
mapped. Probably also what messages are in a receiver's queue. For now, I
postponsed the actual implementation of this, but I have reserved the code.
This is possibly the hardest kernel operation to implement, because a list of
items does not have a hard limit on its size. For other operations, it is
possible to return a value in a register, or in a page (which needs to be
provided by the caller). But in this case, that is not guaranteed to be
possible. So I need to think about how to do this.
\section{A name for the kernel}
However, at this point I am publishing the existence of the kernel, and so I
need to give it a name. I like Greek mythology, so I decided to make it a
Greek god. Because the kernel is mostly doing communication between programs,
while the programs do the real work on the system, I thought of Hermes, the
messenger of the gods. However, I don't really like his name, and I want a
logo which is furrier than a winged boot or staff. So I chose Iris, who is
also a messenger of gods, but she has a rainbow symbol. This is much nicer for
creating a logo.
\section{Device drivers}
It's time to do some real testing of the kernel. So I've read the Linux
keyboard driver source, and implemented the same functionality in a boot
thread. During kernel load, several boot threads are started. At first, it is
just this one.
The keyboard of the device is like any other keyboard, except that it doesn't
have a keyboard controller. So the cpu must do this task itself. A keyboard
is built as a matrix of copper wires, organised in rows and columns. Every
intersection is a key. Pressing the key makes a connection between the row and
the column wire. In the Trendtac, there are 8 rows and 17 columns. All of
these lines go to a general purpose input/output pin on the cpu. The keyboard
driver sets 0 volt on each column in turn, and reads the rows, which are set as
pull-up inputs. If they are not connected, the pull-up makes them return 1.
But if the key of the column which is scanned is pressed, the 0 is connected to
the row line and 0 is read out. Thus the entire keyboard can be read.
Linux does all this in kernel space. That means it can access the GPIO ports
in kseg2 (unmapped and uncached physical memory). In user space, this is not
possible. User space programs can only use mapped memory. So the page with
the GPIO ports needs to be mapped to the device driver's address space. For
this, I added an operation to the thread capability. Not because it has
something to do with a thread, but because every process has its own thread
capability, so no special other capability is needed. I'm adding some more
priviledged operations while I'm at it: allocate physical memory to a Page
object is what I need here. Make a thread ``priviledged'', which means it can
use coprocessor 0, and perform these operations. Get a capability for the top
memory. Register an interrupt handler. I think these should be enough, but I
can always add more, because threads don't need so many operations. I also
added a debug operation, which blinks the lock leds. This operation will be
removed once the display is working.
Writing the keyboard driver was as easy as could be expected: I had some
problems with the meaning of the bits in the registers (does 1 mean input or
output?), and for some reason the above scheme was needed and doing the other
way (scanning the rows and reading the columns) didn't work. But for the rest,
it wasn't very troublesome. And I was happy to see that it is indeed possible
to address device memory through the tlb (so using a mapping). Had that not
been possible, then the device drivers would have been forced into the kernel.
The resulting keyboard driver uses maximum cpu time, because I don't have a
timer interrupt yet, and it flashes the leds when a key is pressed or released,
without telling which key it was. The final driver will be much better. Of
course it will send messages for key events instead of flashing the leds. It
will also be interrupt-driven: when no keys are pressed, all columns will be
set to 0, and all rows will be set to input with pull-up enabled and interrupt
on falling edge. Then no scanning is required. When a key is pressed, the
keyboard will be scanned periodically (on the timer interrupt) until no key is
pressed anymore. It is not possible to use an interrupt-driven approach while
a key is pressed, because there is no way to set up the lines such that there
will always be a change when a key is pressed or released. That's not a
problem: scanning doesn't take much time, and when the keyboard is being used,
the machine is active anyway. While no keys are pressed it makes sense to
minimize power consumption, so then the interrupt-driven approach is more
important.
\section{Display driver}
The next thing to write is a display driver. With a keyboard and a display, it
starts to look like a real computer. However, this proved to be a lot harder
than I expected.
First of all, it wasn't entirely clear which part of the Linux driver I needed
to copy. It has support for many displays on all kinds of mips devices, and I
only want support for the hardware in the machine. After some searching, it
seems that the Trendtac uses the ``pmpv1'' settings.
Now the display consists of two parts: the pixels and the backlight. I started
with the easy part, the backlight. It is connected to a pulse-width-modulator
(pwm) of the cpu. This means that the cpu has some logic to make very fast
pulses of well-defined width. Connecting this to a light allows software to
set the intensity of the output. This means the backlight can be dimmed.
That's nice. Or well, it should be. When copying the Linux code, I can switch
the backlight on and off, but the pwm doesn't seem to work. That's the third
counter\footnote{a pwm is implemented using a counter to determine the pulse
width} that doesn't count: the count register, the random register and the pwm.
\section{Clocks}
Because this didn't feel good, I decided to implement the timer interrupt
first. I copied some code for it from Linux and found, as I feared, that it
didn't give any interrupts. I suppose the os timer isn't running either.
However, it wasn't as bad. I simply had a bug in my timer code; the OS timer
does give interrupts. Checks to see the random register also showed that while
it doesn't run as required by the mips specification, it does auto-increment as
part of the \textit{tlbwr} instruction, which is for practical purposes just as
good (but, I suppose, costs less power).
So the only clock that isn't working is the cpu counter. This means that the
operating system timer must be used for timed interrupts, and that works fine.
After rereading the Linux driver for the display, I also found several things I
had done wrong, and after fixing them it did indeed work. The display
controller reads its data from physical memory, which means that the entire
framebuffer needs to be a continuous part of physical memory. I had to create
a new kernel call for this. Like the other priviledged calls, I added it to
the Thread capability.
\section{Debugging made easier}
So far, all debugging had to be done using blinking LEDs. This is slow and
annoying. With a working display, that was no longer needed. I added a simple
($6\cross8$) character set, and implemented a way to let the kernel send
messages which are printed on the screen. Then I changed the response to a
\textit{break} opcode to result in sending a character to the lcd as well. Now
I have a textual log output, which is much better than blinking LEDs.
Shortly after this, I encountered a bug in the kernel allocation routines.
This still needed to be debugged with blinking LEDs, because allocation was
done as part of sending messages to the display driver. This was annoying, but
now that's done as well and the text log can be used.
\section{Keyboard}
The keyboard driver works mostly as I expected it to. I added interrupts on
any change, so that it is quite normal that key changes are detected by
interrupt, which is faster than waiting for a scan. I would like to use
level-triggered interrupts, instead of edge-triggered. However, at the moment
that doesn't seem to work. I don't really care for now, although this may lead
to missed keys, so it is something to fix eventually.
\section{What is a terminal?}
Now's the time to think about more high-level features. One feature I want to
have is that a user has a session manager. This session manager can have
access to the terminal. And it can lose it. And get it again. It gets access
when the user logs in, and loses it when the user logs out. Having access
means being able to use the hardware (display, keyboard, sound, etc.). The
problem is mostly with losing the display. Getting access to the display
happens by mapping the pages into memory. The user can then share these pages,
and it will be impossible to revoke the access.
But there is a simple solution. The session manager itself is part of the
system. It is trusted by the kernel, and will behave. It will do anything the
user asks, as long as the system allows it. Each session manager can have its
own frame buffer. This is even a good idea: it means that user programs will
not have to handle things differently depending on whether the framebuffer is
available: it is always there, it may just not be visible for the user. Then
the rest of the problem is for the user to solve. The user may mess up their
own display if they want. It will not harm the main control display (used by
session managers and the login manager), or displays of other users.
\section{Defining interfaces}
The next programs to write are a \textit{block device} (the mmc and sd card
driver, or else a ramdisk), a file system, the session manager, a keyboard
translator (interpreting modifier keys and implementing key repeat) and some
sort of shell. These are more device \textit{class} interfaces than simply
interfaces for these specific devices. So it's good to design an interface for
the class, which allows other devices of the same class to use the same
interface. Then higher level programs can use both devices without noticing.
\end{document}

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1
source/gpio.ccp
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@ -1 +0,0 @@
nanonote-gpio.ccp

350
source/gpio.txt
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@ -1,350 +0,0 @@
GPIO control:
#define GPIO_BASE 0xB0010000
#define IRQ_GPIO3 25
#define IRQ_GPIO2 26
#define IRQ_GPIO1 27
#define IRQ_GPIO0 28
#define GPIO_IRQ_LOLEVEL 0
#define GPIO_IRQ_HILEVEL 1
#define GPIO_IRQ_FALLEDG 2
#define GPIO_IRQ_RAISEDG 3
// GP ... Registers: one set for each port of 32 pins; total 128 pins means 4 groups. Total size: 4 * 0x30 == 0xc0.
#define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) // D: data
#define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) // DI: data in: 0 is input; 1 is output. Disable interrupts on the pin before touching this.
#define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) // OD:
#define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) // PU: pull-up (1 is enable)
#define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) // AL: alternate lower: per 2 bit; 00 means use as gpio; other values mean use as alternate function
#define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) // AU: alternate upper: same thing, needs 2 registers because it's 2 bits per pin.
#define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) // IDL: interrupt detect lower: per 2 bit (GPIO_IRQ_*)
#define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) // IDU: interrupt detect upper: same thing, upper 16 bit
#define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) // IE: interrupt enable (0 is disable)
#define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) // IM:
#define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) // F: flag: set on interrupt; cleared by user.
#define IRQ_GPIO_0 48
#define NUM_GPIO 128
// Pins for alternate functions:
#define __gpio_as_ssi() \
do { \
REG_GPIO_GPALR(2) &= 0xFC00FFFF; \
REG_GPIO_GPALR(2) |= 0x01550000; \
} while (0)
#define __gpio_as_uart3() \
do { \
REG_GPIO_GPAUR(0) &= 0xFFFF0000; \
REG_GPIO_GPAUR(0) |= 0x00005555; \
} while (0)
#define __gpio_as_uart2() \
do { \
REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \
REG_GPIO_GPALR(3) |= 0x40000000; \
REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \
REG_GPIO_GPAUR(3) |= 0x04000000; \
} while (0)
#define __gpio_as_uart1() \
do { \
REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \
REG_GPIO_GPAUR(0) |= 0x00050000; \
} while (0)
#define __gpio_as_uart0() \
do { \
REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \
REG_GPIO_GPAUR(3) |= 0x50000000; \
} while (0)
#define __gpio_as_scc0() \
do { \
REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \
REG_GPIO_GPALR(2) |= 0x00000011; \
} while (0)
#define __gpio_as_scc1() \
do { \
REG_GPIO_GPALR(2) &= 0xFFFFFF33; \
REG_GPIO_GPALR(2) |= 0x00000044; \
} while (0)
#define __gpio_as_scc() \
do { \
__gpio_as_scc0(); \
__gpio_as_scc1(); \
} while (0)
#define __gpio_as_dma() \
do { \
REG_GPIO_GPALR(0) &= 0x00FFFFFF; \
REG_GPIO_GPALR(0) |= 0x55000000; \
REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \
REG_GPIO_GPAUR(0) |= 0x00500000; \
} while (0)
#define __gpio_as_msc() \
do { \
REG_GPIO_GPALR(1) &= 0xFFFF000F; \
REG_GPIO_GPALR(1) |= 0x00005550; \
} while (0)
#define __gpio_as_pcmcia() \
do { \
REG_GPIO_GPAUR(2) &= 0xF000FFFF; \
REG_GPIO_GPAUR(2) |= 0x05550000; \
} while (0)
#define __gpio_as_emc(csmask) \
do { \
REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \
REG_GPIO_GPALR(2) |= 0x40000000; \
REG_GPIO_GPAUR(2) &= 0xFFFF0000; \
REG_GPIO_GPAUR(2) |= 0x00005555; \
} while (0)
#define __gpio_as_lcd_slave() \
do { \
REG_GPIO_GPALR(1) &= 0x0000FFFF; \
REG_GPIO_GPALR(1) |= 0x55550000; \
REG_GPIO_GPAUR(1) &= 0x00000000; \
REG_GPIO_GPAUR(1) |= 0x55555555; \
} while (0)
#define __gpio_as_lcd_master() \
do { \
REG_GPIO_GPALR(1) &= 0x0000FFFF; \
REG_GPIO_GPALR(1) |= 0x55550000; \
REG_GPIO_GPAUR(1) &= 0x00000000; \
REG_GPIO_GPAUR(1) |= 0x556A5555; \
} while (0)
#define __gpio_as_usb() \
do { \
REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \
REG_GPIO_GPAUR(0) |= 0x55000000; \
} while (0)
#define __gpio_as_ac97() \
do { \
REG_GPIO_GPALR(2) &= 0xC3FF03FF; \
REG_GPIO_GPALR(2) |= 0x24005400; \
} while (0)
#define __gpio_as_i2s_slave() \
do { \
REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \
REG_GPIO_GPALR(2) |= 0x14005100; \
} while (0)
#define __gpio_as_i2s_master() \
do { \
REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \
REG_GPIO_GPALR(2) |= 0x28005100; \
} while (0)
#define __gpio_as_eth() \
do { \
REG_GPIO_GPAUR(3) &= 0xFC000000; \
REG_GPIO_GPAUR(3) |= 0x01555555; \
} while (0)
#define __gpio_as_pwm() \
do { \
REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \
REG_GPIO_GPAUR(2) |= 0x50000000; \
} while (0)
#define __gpio_as_ps2() \
do { \
REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \
REG_GPIO_GPALR(1) |= 0x00000005; \
} while (0)
#define __gpio_as_uprt() \
do { \
REG_GPIO_GPALR(1) &= 0x0000000F; \
REG_GPIO_GPALR(1) |= 0x55555550; \
REG_GPIO_GPALR(3) &= 0xC0000000; \
REG_GPIO_GPALR(3) |= 0x15555555; \
} while (0)
#define __gpio_as_cim() \
do { \
REG_GPIO_GPALR(0) &= 0xFF000000; \
REG_GPIO_GPALR(0) |= 0x00555555; \
} while (0)
// Pins on the trendtac:
0.00 keyboard
0.01 keyboard
0.02 keyboard
0.03 keyboard
0.04 keyboard
0.05 keyboard
0.06 keyboard
0.07 keyboard
0.08 keyboard interrupt?
0.09
0.10
0.11
0.12
0.13 touchpad right button
0.14
0.15
0.16 touchpad left button
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
0.31
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
2.00 SPEN: lcd enable
2.01 SPCK: lcd clock
2.02 SPDA: lcd data
2.03 LCD_RET: lcd reset
2.04
2.05
2.06
2.07
2.08
2.09
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30 PWM enable (for lcd backlight)
2.31
3.00 keyboard
3.01 keyboard
3.02 keyboard
3.03 keyboard
3.04 keyboard
3.05 keyboard
3.06 keyboard
3.07 keyboard
3.08 keyboard
3.09 keyboard
3.10 keyboard
3.11 keyboard
3.12 keyboard
3.13 keyboard
3.14 keyboard
3.15 keyboard
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29 keyboard
3.30
3.31
Devices enabled in linux:
+ __harb_usb0_uhc();
+ __gpio_as_emc();
+ __gpio_as_uart0();
+ __gpio_as_dma();
+ __gpio_as_eth();
+ __gpio_as_usb();
+ __gpio_as_lcd_master();
+#if defined(CONFIG_I2S_AK4642EN)
+//wjx __gpio_as_scc1();
+ __gpio_as_i2s_master(); //wjx
+#endif
+#if defined(CONFIG_I2S_TSC2301) || defined(CONFIG_I2S_TLC320AIC23)
+ __gpio_as_ssi();
+#endif
+ //__gpio_as_ac97();
+#if defined(CONFIG_I2S_TSC2301) || defined(CONFIG_I2S_TLC320AIC23) || defined(CONFIG_I2S_CS42L51)
+ __gpio_as_i2s_slave();
+#endif
+//wjx __gpio_as_cim();
+ __gpio_as_msc();
+
+/* wjx
+ __gpio_as_output(GPIO_LED_EN);
+ __gpio_set_pin(GPIO_LED_EN);
+
+ __gpio_as_output(GPIO_DISP_OFF_N);
+ __gpio_set_pin(GPIO_DISP_OFF_N);
+*/
+ __gpio_as_output(GPIO_PWM0);
+ __gpio_set_pin(GPIO_PWM0);
+
+
+//wjx __gpio_as_input(GPIO_RTC_IRQ);
+ __gpio_as_output(GPIO_USB_CLK_EN);
+ __gpio_set_pin(GPIO_USB_CLK_EN);

6
source/alarm.ccp → userspace/application/alarm.ccp
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@ -1,4 +1,5 @@
#pypp 0
// vim: set filetype=cpp : //
#include <iris.hh>
#include <devices.hh>
@ -23,16 +24,15 @@ Iris::Num start ():
Iris::my_parent.provide_capability <Iris::Event> (self)
cap = Iris::my_receiver.create_capability (INTERRUPT)
Iris::my_parent.init_done ()
font.printf ("Press a key to attempt reboot.\n")
while true:
Iris::wait ()
switch Iris::recv.protected_data.l:
case INTERRUPT:
// Interrupt
// RTC alarm interrupt.
if Iris::recv.data[0].l == ~0:
// Not a real interrupt, just an abort notification.
continue
font.printf ("alarm: interrupt\n")
font.printf ("alarm: RTC alarm interrupt\n")
break
case CONTROL:
// Store callback

0
source/ball.ccp → userspace/application/ball.ccp
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0
source/booter.ccp → userspace/application/booter.ccp
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0
source/bsquare.ccp → userspace/application/bsquare.ccp
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0
source/metronome.ccp → userspace/application/metronome.ccp
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0
source/test.ccp → userspace/application/test.ccp
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5
source/bootinit.ccp → userspace/boot/bootinit.ccp
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@ -320,15 +320,10 @@ Iris::Num start ():
Iris::Memory top_memory = Iris::get_top_memory ()
Iris::Directory root = receive_devices ()
root.lock_ro ()
kdebug_line ()
Iris::Block run_block = find (root, ELFRUN_NAME)
kdebug_line ()
Iris::Cap parent_cap = Iris::my_receiver.create_capability (0)
kdebug_line ()
run (run_block, top_memory, parent_cap)
kdebug_line ()
Iris::wait ()
kdebug_line ()
if Iris::recv.data[0].l != Iris::Parent::PROVIDE_CAPABILITY || Iris::recv.data[1].l != Iris::Elfrun::ID:
Iris::panic (0, "elfrun doesn't provide correct capability")
Iris::Cap reply = Iris::get_reply ()

0
source/crt0.ccp → userspace/boot/crt0.ccp
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0
source/init.ccp → userspace/boot/init.ccp
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8
mkthreadlist → userspace/boot/mkthreadlist
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@ -1,4 +1,4 @@
#!/bin/sh
#!/bin/bash
cat << EOF
.globl init_start
.globl thread_start
@ -8,8 +8,8 @@ EOF
for i in "$@" ; do
cat << EOF
$i:
.incbin "fs/$i.elf"
${i##*/}:
.incbin "fs/${i##*/}.elf"
.balign 0x1000
EOF
done
@ -22,7 +22,7 @@ EOF
for i in "$@" ; do
cat << EOF
.word $i
.word ${i##*/}
EOF
done

0
source/charset → userspace/data/charset
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0
courier-10+8+32.png → userspace/data/courier-10+8+32.png
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0
courier.xcf → userspace/data/courier.xcf
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0
init.config → userspace/data/init.config
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0
makefont → userspace/data/makefont
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0
source/buffer.ccp → userspace/glue/buffer.ccp
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0
source/elfrun.ccp → userspace/glue/elfrun.ccp
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0
source/fat.ccp → userspace/glue/fat.ccp
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0
source/font.ccp → userspace/glue/font.ccp
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0
source/gui.ccp → userspace/glue/gui.ccp
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0
source/partition.ccp → userspace/glue/partition.ccp
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0
source/usbmassstorage.ccp → userspace/glue/usbmassstorage.ccp
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1
userspace/hardware Symbolic link
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@ -0,0 +1 @@
nanonote

0
source/boot.ccp → userspace/nanonote/boot.ccp
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0
source/buzzer.ccp → userspace/nanonote/buzzer.ccp
View File

0
source/nanonote-gpio.ccp → userspace/nanonote/gpio.ccp
View File

2
source/lcd.ccp → userspace/nanonote/lcd.ccp
View File

@ -20,7 +20,7 @@
#define ARCH
#include "arch.hh"
__asm__ volatile (".section .rodata\n.globl charset\ncharset:\n.incbin \"source/charset.data\"\n.section .text")
__asm__ volatile (".section .rodata\n.globl charset\ncharset:\n.incbin \"source/data/charset.data\"\n.section .text")
extern unsigned char const charset[127-32][8][6]
#define assert(x) do { if (!(x)) { kdebug ("assertion failed " #x); while (true) {} } } while (0)

0
source/nand.ccp → userspace/nanonote/nand.ccp
View File

18
source/rtc.ccp → userspace/nanonote/rtc.ccp
View File

@ -54,6 +54,8 @@ Iris::Num start ():
ready ()
rtc_set_alarm_second (0)
ready ()
rtc_set_scratch_pattern (0xbeefface)
ready ()
rtc_disable_alarm ()
ready ()
rtc_clear_alarm_flag ()
@ -62,13 +64,11 @@ Iris::Num start ():
ready ()
rtc_disable_1Hz_irq ()
ready ()
rtc_set_hwfcr_val (0)
rtc_set_hwfcr_val (0x1e0)
ready ()
rtc_set_hrcr_val (0)
rtc_set_hrcr_val (0xfe0)
ready ()
rtc_enable_alarm_wakeup ()
ready ()
rtc_set_scratch_pattern (0xbeefface)
rtc_disable_alarm_wakeup ()
Iris::RTC self = Iris::my_receiver.create_capability (1)
Iris::my_parent.provide_capability <Iris::RTC> (self.copy ())
Iris::free_cap (self)
@ -81,6 +81,8 @@ Iris::Num start ():
// Interrupt.
ready ()
rtc_disable_alarm ()
ready ()
rtc_disable_alarm_wakeup ()
if have_interrupt:
interrupt.invoke (0)
Iris::free_cap (interrupt)
@ -118,14 +120,14 @@ Iris::Num start ():
Iris::unregister_interrupt (IRQ_RTC)
ready ()
rtc_disable_alarm ()
ready ()
rtc_disable_alarm_wakeup ()
reply.invoke ()
Iris::free_cap (reply)
case Iris::RTC::SET_ALARM:
Iris::Cap reply = Iris::get_reply ()
Iris::Cap arg = Iris::get_arg ()
unsigned alarm = Iris::recv.data[1].l
ready ()
rtc_clear_alarm_flag ()
if have_interrupt:
Iris::debug ("not registering irq\n")
interrupt.invoke (~0)
@ -141,6 +143,8 @@ Iris::Num start ():
rtc_clear_alarm_flag ()
ready ()
rtc_enable_alarm ()
ready ()
rtc_enable_alarm_wakeup ()
reply.invoke ()
Iris::free_cap (reply)
break

0
source/sdmmc.ccp → userspace/nanonote/sdmmc.ccp
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1
source/udc.ccp → userspace/nanonote/udc.ccp
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@ -552,7 +552,6 @@ enum pdata:
NAME
Iris::Num start ():
Iris::debug ("udc started")
map_udc ()
map_gpio ()
map_cpm ()

0
source/trendtac-gpio.ccp → userspace/trendtac/trendtac-gpio.ccp
View File