#pypp 0
#include "kernel.hh"

// hi and lo cannot be saved in assemply due to space restrictions.
#define save_hilo(x) do { __asm__ volatile ("mfhi %0 ; mflo %1" : "=r"((x)->arch.hi), "=r"((x)->arch.lo)); } while (0)

/// A TLB miss has occurred.  This should eventually move to entry.S.
Thread *tlb_refill (Thread *current, unsigned EntryHi):
	save_hilo (current)
	Page ***dir = current->address_space->arch.directory
	if !dir:
		panic (0x00000000, "no page directory for thread")
	EntryHi >>= 12
	Page **table = dir[EntryHi >> 10]
	if !table:
		panic (0x11111111, "no page table at requested address")
	EntryHi &= (1 << 10) - 1
	Page *page0 = table[EntryHi & ~1]
	Page *page1 = table[EntryHi | 1]
	if (!(EntryHi & 1) && !page0) || ((EntryHi & 1) && !page1):
		panic (0x22222222, "no page mapped at requested address")
	unsigned low0, low1
	if page0:
		low0 = (unsigned)page0->physical | 0x18 | 0x4 | 0x2
	else
		low0 = 0
	if page1:
		low1 = (unsigned)page1->physical | 0x18 | 0x4 | 0x2
	else
		low1 = 0
	__asm__ volatile ("mtc0 %0, $2; mtc0 %1, $3; tlbwr" :: "r"(low0), "r"(low1))
	return current

/// An interrupt which is not an exception has occurred.
Thread *interrupt (Thread *current):
	save_hilo (current)
	return current

/// A general exception has occurred.
Thread *exception (Thread *current):
	save_hilo (current)
	panic (0xdeadbeaf, "exception")
	return current

/// There's a cache error.  Big trouble.  Probably not worth trying to recover.
Thread *cache_error (Thread *current):
	save_hilo (current)
	panic (0x33333333, "cache error")
	return current