cclk: cpu clock.  Fastest clock in the system.
hclk: high-speed peripheral bus clock.
pclk: peripheral bus clock.
mclk: memory clock, for emc.
ldclk: lcd device clock.
lpclk: lcd pixel clock.
cim_mclk: clock output for cim.
cim_pclk: clock input for cim.
i2sclk: codec clock.
mscclk: msc clock.
ssiclk: ssi clock.
exclk: 12MHz clock output, used by uart, i2c, ssi, tcu, usb2.0-phy.
rtclk: 32768Hz clock input for rtc.

cclk: 252M
hclk: 84M
pclk: 84M
mclk: 84M
ldclk: 84M; must not be larger than 150M
lpclk: 25295340 (70Hz screen refresh)
cim_mclk: not used.
cim_pclk: not used.
i2sclk: must be 12M
mscclk: must not be larger than 400k during init; not larger than 25M later.
ssiclk: not used.
exclk: 12M, not adjustable.
rtclk: 32768, not adjustable.

usb clock, for host and device, must be 48M.

restrictions:
- cclk must be i*hclk
- i must not be 24 or 32
- hclk = mclk or hclk = 2*mclk
- mclk = k*pclk

so:
- pclk is set
- mclk = k*pclk
- hclk = l*mclk = l*k*pclk; l = 1 or 2
- cclk = i*hclk = i*l*k*pclk; i != 24 or 32

In the code:
m = 42
n = 2
no = 1
So clkout = 12M * 21 = 252M; this is the pll clock frequency.