#pypp 0
// Iris: micro-kernel for a capability-based operating system.
// mips/nanonote/sdram-setup.ccp: bootstrapping over usb.
// Copyright 2009 Bas Wijnen <wijnen@debian.org>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.

// This runs like the kernel.  In particular, it doesn't want userspace declarations.
#define __KERNEL
#include "jz4740.hh"

#define CONFIG_NR_DRAM_BANKS    1       // SDRAM BANK Number: 1, 2
#define SDRAM_CASL              3       // CAS latency: 2 or 3
// SDRAM Timings, unit: ns
#define SDRAM_TRAS              45      // RAS# Active Time
#define SDRAM_RCD               20      // RAS# to CAS# Delay
#define SDRAM_TPC               20      // RAS# Precharge Time
#define SDRAM_TRWL              7       // Write Latency Time
#define SDRAM_TREF              15625   // Refresh period: 4096 refresh cycles/64ms

asm volatile (".set noreorder\n"
		"\t.globl __start\n"
		"\t.text\n"
		"__start:\n"
		"\tla $sp, 0x80004000\n"
		"__hack_label:\n"
		"\tmove $a0, $ra\n"
		"\tbal 1f\n"
		"\tnop\n"
		"\t.word _gp\n"
		"1:\n"
		"\tlw $gp, 0($ra)\n"
		"\tla $t9, start_cpp\n"
		"\tmove $ra, $a0\n"
		"\tjr $t9\n"
		"\tnop\n"
		".set reorder")

extern "C":
	void start_cpp ()

void start_cpp ():
	unsigned dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns
	unsigned cas_latency_sdmr[2] = { EMC_SDMR_CAS_2, EMC_SDMR_CAS_3 }
	unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT }
	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}

	cpu_clk = 225000000
	gpio_as_sdram_32bit ()
	unsigned SDRAM_BW16 = 0
	unsigned SDRAM_BANK4 = 1
	unsigned SDRAM_ROW = 13
	unsigned SDRAM_COL = 9

	mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()]
	EMC_BCR = 0
	EMC_RTCSR = 0
	#define SDRAM_ROW0    11
	#define SDRAM_COL0     8
	#define SDRAM_BANK40   0
	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
	// Basic DMCR value
	dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
	// SDRAM timimg
	ns = 1000000000 / mem_clk
	tmp = SDRAM_TRAS / ns
	if tmp < 4:
		tmp = 4
	if tmp > 11:
		tmp = 11
	dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT)
	tmp = SDRAM_RCD/ns
	if tmp > 3:
		tmp = 3
	dmcr |= (tmp << EMC_DMCR_RCD_BIT)
	tmp = SDRAM_TPC/ns
	if tmp > 7:
		tmp = 7
	dmcr |= (tmp << EMC_DMCR_TPC_BIT)
	tmp = SDRAM_TRWL/ns
	if tmp > 3:
		tmp = 3
	dmcr |= (tmp << EMC_DMCR_TRWL_BIT)
	tmp = (SDRAM_TRAS + SDRAM_TPC)/ns
	if tmp > 14:
		tmp = 14
	dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT)

	// SDRAM mode value
	sdmode = EMC_SDMR_BT_SEQ | EMC_SDMR_OM_NORMAL | EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];

	// Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0
	EMC_DMCR = dmcr
	REG8(EMC_SDMR0|sdmode) = 0

	// Wait for precharge, > 200us
	tmp = (cpu_clk / 1000000) * 1000
	volatile unsigned t = tmp
	while t--:

	// Stage 2. Enable auto-refresh
	EMC_DMCR = dmcr | EMC_DMCR_RFSH

	tmp = SDRAM_TREF/ns
	tmp = tmp/64 + 1
	if tmp > 0xff:
		tmp = 0xff
	EMC_RTCOR = tmp
	EMC_RTCNT = 0
	// Divisor is 64, CKO/64
	EMC_RTCSR = EMC_RTCSR_CKS_64

	// Wait for number of auto-refresh cycles
	tmp = (cpu_clk / 1000000) * 1000
	t = tmp
	while t--:

	// Stage 3. Mode Register Set
	EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET
	REG8(EMC_SDMR0|sdmode) = 0

	// Set back to basic DMCR value
	EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET

	// everything is ok now: return to boot loader to load stage 2.