mirror of
git://projects.qi-hardware.com/iris.git
synced 2024-07-02 20:14:11 +03:00
137 lines
3.5 KiB
COBOL
137 lines
3.5 KiB
COBOL
#pypp 0
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#define ARCH
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#include "kernel.hh"
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/// A TLB miss has occurred. This should eventually move to entry.S.
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Thread *tlb_refill ():
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//panic (0x88776655, "TLB refill")
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unsigned EntryHi
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cp0_get (CP0_ENTRY_HI, EntryHi)
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Page *page0 = current->address_space->get_mapping (EntryHi & ~(1 << 12))
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Page *page1 = current->address_space->get_mapping (EntryHi | (1 << 12))
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if (!(EntryHi & (1 << 12)) && !page0) || ((EntryHi & (1 << 12)) && !page1):
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panic (0x22222222, "no page mapped at requested address")
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unsigned low0, low1
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if page0:
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low0 = (unsigned)page0->physical | 0x18 | 0x4 | 0x2
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else
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low0 = 0
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if page1:
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low1 = (unsigned)page1->physical | 0x18 | 0x4 | 0x2
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else
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low1 = 0
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cp0_set (CP0_ENTRY_LO0, low0)
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cp0_set (CP0_ENTRY_LO1, low1)
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__asm__ volatile ("tlbwr")
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return current
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/// An interrupt which is not an exception has occurred.
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Thread *interrupt ():
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panic (0x88877722)
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unsigned cause
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cp0_get (CP0_CAUSE, cause)
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for unsigned i = 0; i < 8; ++i:
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if cause & (1 << (i + 8)):
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// TODO: Handle interrupt.
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// Disable all interrupts which are not handled.
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unsigned status
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cp0_get (CP0_STATUS, status)
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cp0_get (CP0_CAUSE, cause)
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status &= ~(cause & 0x0000ff00)
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cp0_set (CP0_STATUS, status)
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return current
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/// A general exception has occurred.
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Thread *exception ():
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unsigned cause
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cp0_get (CP0_CAUSE, cause)
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switch (cause >> 2) & 0x1f:
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case 0:
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// Interrupt.
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panic (0x11223344, "Interrupt.")
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case 1:
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// TLB modification.
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panic (0x21223344, "TLB modification.")
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case 2:
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//unsigned a
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//cp0_get (CP0_EPC, a)
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//panic (a)
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// TLB load or instruction fetch.
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panic (0x31223344, "TLB load or instruction fetch.")
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case 3:
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unsigned a
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cp0_get (CP0_EPC, a)
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panic (a)
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// TLB store.
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panic (0x41223344, "TLB store.")
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case 4:
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// Address error load or instruction fetch.
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panic (0x51223344, "Address error load or instruction fetch.")
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case 5:
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// Address error store.
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panic (0x61223344, "Address error store.")
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case 6:
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// Bus error instruction fetch.
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panic (0x71223344, "Bus error instruction fetch.")
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case 7:
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// Bus error load or store.
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panic (0x81223344, "Bus error load or store.")
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case 8:
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// Syscall.
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// DEBUG: allow new exceptions.
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//cp0_set0 (CP0_STATUS)
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arch_invoke ()
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return current
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case 9:
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// Breakpoint.
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panic (0x91223344, "Breakpoint.")
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case 10:
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// Reserved instruction.
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panic (*(unsigned *)0x004000b0)
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panic (0xa1223344, "Reserved instruction.")
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case 11:
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// Coprocessor unusable.
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panic (0xb1223344, "Coprocessor unusable.")
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case 12:
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// Arithmetic overflow.
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panic (0xc1223344, "Arithmetic overflow.")
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case 13:
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// Trap.
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panic (0xe1223344, "Trap.")
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case 15:
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// Floating point exception.
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panic (0xf1223344, "Floating point exception.")
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case 23:
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// Reference to WatchHi/WatchLo address.
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panic (0xf2223344, "Reference to WatchHi/WatchLo address.")
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case 24:
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// Machine check.
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panic (0xf3223344, "Machine check.")
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case 30:
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// Cache error (EJTAG only).
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panic (0xf4223344, "Cache error (EJTAG only).")
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case 14:
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 31:
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// Reserved.
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panic (0xf5223344, "Reserved exception code")
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default:
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panic (0xf6223344, "Impossible exception code")
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return current
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/// There's a cache error. Big trouble. Probably not worth trying to recover.
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Thread *cache_error ():
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panic (0x33333333, "cache error")
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return current
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