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git://projects.qi-hardware.com/iris.git
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52 lines
1.5 KiB
COBOL
52 lines
1.5 KiB
COBOL
#pypp 0
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#include "kernel.hh"
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// hi and lo cannot be saved in assemply due to space restrictions.
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#define save_hilo(x) do { __asm__ volatile ("mfhi %0 ; mflo %1" : "=r"((x)->cpu.hi), "=r"((x)->cpu.lo)); } while (0)
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/// A TLB miss has occurred. This should eventually move to entry.S.
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Thread *tlb_refill (Thread *current, unsigned EntryHi):
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save_hilo (current)
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led (false, false)
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Page ***dir = current->address_space->cpu.directory
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if !dir:
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panic (0x00000000, "no page directory for thread")
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EntryHi >>= 12
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Page **table = dir[EntryHi >> 10]
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if !table:
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panic (0x11111111, "no page table at requested address")
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EntryHi &= (1 << 10) - 1
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Page *page0 = table[EntryHi & ~1]
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Page *page1 = table[EntryHi | 1]
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if (!(EntryHi & 1) && !page0) || ((EntryHi & 1) && !page1):
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panic (0x22222222, "no page mapped at requested address")
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unsigned low0, low1
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if page0:
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low0 = page0->physical | 0x18 | 0x4 | 0x2
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else
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low0 = 0
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if page1:
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low1 = page1->physical | 0x18 | 0x4 | 0x2
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else
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low1 = 0
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__asm__ volatile ("mtc0 %0, $2; mtc0 %1, $3; tlbwr" :: "r"(low0), "r"(low1))
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return current
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/// An interrupt which is not an exception has occurred.
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Thread *interrupt (Thread *current):
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save_hilo (current)
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led (false, false)
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return current
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/// A general exception has occurred.
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Thread *exception (Thread *current):
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save_hilo (current)
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panic (0xdeadbeaf, "exception")
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return current
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/// There's a cache error. Big trouble. Probably not worth trying to recover.
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Thread *cache_error (Thread *current):
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save_hilo (current)
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panic (0x33333333, "cache error")
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return current
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