iris/mips/interrupts.ccp

#pypp 0
// Iris: micro-kernel for a capability-based operating system.
// mips/interrupts.ccp: Functions called by mips/entry.S.
// Copyright 2009 Bas Wijnen <wijnen@debian.org>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.

#define ARCH
#include "../kernel.hh"

typedef unsigned cacheline[8]
void arch_flush_cache ():
	for cacheline *line = (cacheline *)0x80000000; line < (cacheline *)0x80008000; ++line:
		__asm__ volatile ("lw $k0, %0; cache 0, 0($k0); cache 1, 0($k0)" :: "m"(line))

static void handle_exit ():
	if !current || (current == &idle):
		schedule ()
		if !current:
			current = &idle
	if (current->flags & (THREAD_FLAG_RUNNING | THREAD_FLAG_WAITING)) != THREAD_FLAG_RUNNING:
		panic (current->flags, "non-scheduled thread running")
		if !current:
			current = &idle
	if old_current == current:
		return
	arch_flush_cache ()
	if current != &idle:
		if (Memory *)asids[current->address_space->arch.asid] != current->address_space:
			if asids[0]:
				current->address_space->arch.asid = asids[0]
				asids[0] = asids[asids[0]]
			else:
				static unsigned random = 1
				current->address_space->arch.asid = random
				// Overwrite used asid, so flush those values from tlb.
				flush_tlb (random)
				++random
				if random >= 64:
					random = 1
			asids[current->address_space->arch.asid] = (unsigned)current->address_space
	cp0_set (CP0_ENTRY_HI, current->address_space->arch.asid)
	directory = current->address_space->arch.directory
	if current->flags & THREAD_FLAG_PRIV:
		cp0_set (CP0_STATUS, 0x1000ff13)
	else:
		cp0_set (CP0_STATUS, 0x0000ff13)

/// A TLB miss has occurred.  This is the slow version.  It is only used
/// when k0 or k1 is not 0, or when an error occurs.
/// Otherwise, the ultra-fast code in entry.S is used.
Thread *tlb_refill ():
	old_current = current
	if !directory:
		unsigned addr
		cp0_get (CP0_BAD_V_ADDR, addr)
		current->raise (ERR_NO_PAGE_DIRECTORY, addr)
		handle_exit ()
		return current
	unsigned EntryHi
	cp0_get (CP0_ENTRY_HI, EntryHi)
	unsigned *t = directory[EntryHi >> 21]
	if !t:
		unsigned addr
		cp0_get (CP0_BAD_V_ADDR, addr)
		current->raise (ERR_NO_PAGE_TABLE, addr)
	else:
		// - 2 instead of - 1 means reset bit 0
		unsigned idx = (EntryHi >> 12) & ((1 << 9) - 2)
		cp0_set (CP0_ENTRY_LO0, t[idx])
		cp0_set (CP0_ENTRY_LO1, t[idx + 1])
		__asm__ volatile ("tlbwr")
	handle_exit ()
	return current

/// An interrupt which is not an exception has occurred.
Thread *interrupt ():
	old_current = current
	unsigned ipr = INTC_IPR
	for unsigned i = 0; i < 32; ++i:
		if ipr & (1 << i):
			// Handle timer interrupts specially: don't disable them.
			if i == IRQ_OST0:
				continue
			// Disable the interrupt while handling it.
			intc_mask_irq (i)
			intc_ack_irq (i)
			// Send message to interrupt handler.
			if arch_interrupt_receiver[i]:
				Capability::Context c
				for unsigned j = 0; j < 4; ++j:
					c.data[j] = 0
					c.cap[j].reset ()
					c.copy[j] = false
				arch_interrupt_receiver[i]->send_message (i, &c)
				arch_interrupt_receiver[i] = NULL
	if ipr & (1 << IRQ_OST0):
		ost_clear_uf (0)
		intc_ack_irq (IRQ_OST0)
		timer_interrupt ()
	handle_exit ()
	return current

void flush_tlb (unsigned asid):
	for unsigned tlb = 1; tlb < 32; ++tlb:
		cp0_set (CP0_INDEX, tlb)
		__asm__ volatile ("tlbr")
		unsigned hi
		cp0_get (CP0_ENTRY_HI, hi)
		if (hi & 0x1f) == asid:
			// Set asid to 0, which is only used by the idle task.
			cp0_set (CP0_ENTRY_HI, 0x2000 * tlb)
			__asm__ volatile ("tlbwi")

static void arch_invoke ():
	CapRef target
	bool wait
	target = old_current->find_capability (old_current->arch.v0, &wait)
	do_schedule = false
	if wait:
		bool dummy
		CapRef c0, c1, c2, c3
		c0 = old_current->find_capability (old_current->arch.t4, &dummy)
		c1 = old_current->find_capability (old_current->arch.t5, &dummy)
		c2 = old_current->find_capability (old_current->arch.t6, &dummy)
		c3 = old_current->find_capability (old_current->arch.t7, &dummy)
		old_current->wait (c0, c1, c2, c3)
	if !target:
		if (old_current->arch.v0 & ~CAPABILITY_COPY) != ~CAPABILITY_COPY:
			panic (old_current->arch.v0, "debug")
		// There must be no action here.
		return
	Capability::Context c
	c.cap[0] = old_current->find_capability (old_current->arch.a0, &c.copy[0])
	c.cap[1] = old_current->find_capability (old_current->arch.a1, &c.copy[1])
	c.cap[2] = old_current->find_capability (old_current->arch.a2, &c.copy[2])
	c.cap[3] = old_current->find_capability (old_current->arch.a3, &c.copy[3])
	c.data[0] = old_current->arch.t0
	c.data[1] = old_current->arch.t1
	c.data[2] = old_current->arch.t2
	c.data[3] = old_current->arch.t3
	target->invoke (&c)
	if do_schedule && !wait:
		// If the call was to schedule without wait, it isn't done yet.
		schedule ()
	else if old_current != current && (old_current->flags & (THREAD_FLAG_RUNNING | THREAD_FLAG_WAITING)) == THREAD_FLAG_RUNNING:
		// If the caller received an immediate reply from the kernel, it is no longer set as current.  Don't let it lose its timeslice.
		current = old_current

/// A general exception has occurred.
Thread *exception ():
	old_current = current
	unsigned cause
	cp0_get (CP0_CAUSE, cause)
	switch (cause >> 2) & 0x1f:
		case 0:
			// Interrupt.  This shouldn't happen, since CAUSE[IV] == 1.
			panic (0, "Interrupt on exception vector.")
			break
		case 1:
			// TLB modification.
			unsigned addr
			cp0_get (CP0_BAD_V_ADDR, addr)
			current->raise (ERR_WRITE_DENIED, addr)
			break
		case 2:
			// TLB load or instruction fetch.
			unsigned addr
			cp0_get (CP0_BAD_V_ADDR, addr)
			current->raise (ERR_UNMAPPED_READ, addr)
			break
		case 3:
			// TLB store.
			unsigned addr
			cp0_get (CP0_BAD_V_ADDR, addr)
			current->raise (ERR_UNMAPPED_WRITE, addr)
			break
		case 4:
			// Address error load or instruction fetch.
			unsigned addr
			cp0_get (CP0_BAD_V_ADDR, addr)
			current->raise (ERR_INVALID_ADDRESS_READ, addr)
			break
		case 5:
			// Address error store.
			unsigned addr
			cp0_get (CP0_BAD_V_ADDR, addr)
			current->raise (ERR_INVALID_ADDRESS_WRITE, addr)
			break
		case 6:
			// Bus error instruction fetch.
			panic (0, "Bus error instruction fetch.")
			break
		case 7:
			// Bus error load or store.
			panic (0, "Bus error load or store.")
			break
		case 8:
			// Syscall.
			current->pc += 4
			arch_invoke ()
			break
		case 9:
			// Breakpoint.
			#if 0
			current->raise (ERR_BREAKPOINT, 0)
			#else
			current->pc += 4
			if current->arch.a0:
				if dbg_cap:
					panic (0, "Break instruction while log capability was already set")
					break
				bool dummy
				dbg_cap = current->find_capability (current->arch.a1, &dummy)
				if !dbg_cap:
					panic (0, "no log capability provided")
					break
				break
			if dbg_cap:
				dbg_log_char (current->arch.a1)
				break
			break
			#endif
		case 10:
			// Reserved instruction.
			current->raise (ERR_RESERVED_INSTRUCTION, 0)
			break
		case 11:
			// Coprocessor unusable.
			current->raise (ERR_COPROCESSOR_UNUSABLE, 0)
			break
		case 12:
			// Arithmetic overflow.
			current->raise (ERR_OVERFLOW, 0)
			break
		case 13:
			// Trap.
			current->raise (ERR_TRAP, 0)
			break
		case 15:
			// Floating point exception.
			panic (0xe1223344, "Floating point exception.")
			break
		case 23:
			// Reference to WatchHi/WatchLo address.
			current->raise (ERR_WATCHPOINT, 0)
			break
		case 24:
			// Machine check.
			panic (0xf3223344, "Machine check.")
			break
		case 30:
			// Cache error (EJTAG only).
			panic (0xf4223344, "Cache error (EJTAG only).")
			break
		case 14:
		case 16:
		case 17:
		case 18:
		case 19:
		case 20:
		case 21:
		case 22:
		case 25:
		case 26:
		case 27:
		case 28:
		case 29:
		case 31:
			// Reserved.
			panic (0xf5223344, "Reserved exception code")
			break
		default:
			panic (0xf6223344, "Impossible exception code")
			break
	handle_exit ()
	return current

/// There's a cache error.  Big trouble.  Probably not worth trying to recover.
Thread *cache_error ():
	panic (0x33333333, "cache error")
	old_current = current
	handle_exit ()
	return current