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48 lines
1.1 KiB
Plaintext
48 lines
1.1 KiB
Plaintext
cclk: cpu clock. Fastest clock in the system.
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hclk: high-speed peripheral bus clock.
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pclk: peripheral bus clock.
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mclk: memory clock, for emc.
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ldclk: lcd device clock.
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lpclk: lcd pixel clock.
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cim_mclk: clock output for cim.
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cim_pclk: clock input for cim.
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i2sclk: codec clock.
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mscclk: msc clock.
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ssiclk: ssi clock.
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exclk: 12MHz clock output, used by uart, i2c, ssi, tcu, usb2.0-phy.
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rtclk: 32768Hz clock input for rtc.
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cclk: 252M
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hclk: 84M
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pclk: 84M
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mclk: 84M
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ldclk: 84M; must not be larger than 150M
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lpclk: 25295340 (70Hz screen refresh)
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cim_mclk: not used.
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cim_pclk: not used.
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i2sclk: must be 12M
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mscclk: must not be larger than 400k during init; not larger than 25M later.
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ssiclk: not used.
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exclk: 12M, not adjustable.
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rtclk: 32768, not adjustable.
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usb clock, for host and device, must be 48M.
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restrictions:
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- cclk must be i*hclk
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- i must not be 24 or 32
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- hclk = mclk or hclk = 2*mclk
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- mclk = k*pclk
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so:
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- pclk is set
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- mclk = k*pclk
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- hclk = l*mclk = l*k*pclk; l = 1 or 2
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- cclk = i*hclk = i*l*k*pclk; i != 24 or 32
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In the code:
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m = 42
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n = 2
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no = 1
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So clkout = 12M * 21 = 252M; this is the pll clock frequency.
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