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git://projects.qi-hardware.com/iris.git
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231 lines
4.0 KiB
ArmAsm
231 lines
4.0 KiB
ArmAsm
// The kernel stack.
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.lcomm kernel_stack, KERNEL_STACK_SIZE
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.globl __start
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.globl run_idle
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.set noat
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.set noreorder
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#define EntryLo0 2
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#define EntryLo1 3
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#define EntryHi 10
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#define Random 1
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#define Index 0
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#define PageMask 5
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#define Wired 6
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#define Config 16
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#define Status 12
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#define Cause 13
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#define Compare 11
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#define save_regs \
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sw $k0, -0x180($zero) ;\
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lw $k0, -0x184($zero) ;\
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sw $at, 12($k0) ;\
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sw $k1, 108($k0) ;\
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lw $k1, -0x180($zero) ;\
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sw $k1, 104($k0) ;\
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sw $v0, 16($k0) ;\
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sw $v1, 20($k0) ;\
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sw $t0, 40($k0) ;\
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sw $sp, 84($k0) ;\
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sw $fp, 88($k0) ;\
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sw $ra, 92($k0) ;\
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lw $gp, -12($zero) ;\
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la $sp, kernel_stack + KERNEL_STACK_SIZE ;\
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move $a0, $k0 ;\
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la $ra, kernel_exit ;\
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bal save_args
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#define restore_regs \
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lw $v0, 96($k0) ;\
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lw $v1, 100($k0) ;\
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mthi $v0 ;\
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mtlo $v1 ;\
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lw $v0, 16($k0) ;\
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lw $v1, 20($k0) ;\
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lw $a0, 24($k0) ;\
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lw $a1, 28($k0) ;\
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lw $a2, 32($k0) ;\
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lw $a3, 36($k0) ;\
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lw $t0, 40($k0) ;\
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lw $t1, 44($k0) ;\
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lw $t2, 48($k0) ;\
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lw $t3, 52($k0) ;\
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lw $t4, 56($k0) ;\
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lw $t5, 60($k0) ;\
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lw $t6, 64($k0) ;\
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lw $t7, 68($k0) ;\
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lw $t8, 72($k0) ;\
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lw $t9, 76($k0) ;\
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lw $gp, 80($k0) ;\
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lw $sp, 84($k0) ;\
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lw $fp, 88($k0) ;\
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lw $ra, 92($k0) ;\
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lw $at, 12($k0) ;\
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lw $k1, 104($k0) ;\
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sw $k1, -0x180($zero) ;\
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lw $k1, 108($k0) ;\
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sw $k0, -0x184($zero) ;\
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lw $k0, -0x180($zero)
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addr_000:
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// TLB refill
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// TODO: this should probably be assembly-only for speed reasons
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li $a0, 0xffff0000
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la $t9, panic
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jr $t9
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save_regs
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mfc0 $a1, $EntryHi
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la $t9, tlb_refill
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jr $t9
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nop
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.fill 0x100 - (. - addr_000)
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addr_100:
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// Cache error
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// TODO
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li $a0, 0xaaaa0000
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la $t9, panic
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jr $t9
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save_regs
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la $t9, cache_error
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jr $t9
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nop
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.fill 0x180 - (. - addr_000)
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addr_180:
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// General exception
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// TODO
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li $a0, 0xaaff0000
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la $t9, panic
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jr $t9
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save_regs
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la $t9, exception
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jr $t9
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nop
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.fill 0x200 - (. - addr_000)
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addr_200:
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// Interrupt
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// TODO
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li $a0, 0x0a0f0000
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la $t9, panic
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jr $t9
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save_regs
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la $t9, interrupt
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jr $t9
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nop
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.fill 0x280 - (. - addr_000)
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// space for save_regs.
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.word 0
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.word 0
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start_idle:
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b .
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nop
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.word idle_page
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.word 0x80000000 // A pointer to the current page.
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__start:
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bal 1f
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nop
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.word _gp
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// For some reason the disassembler considers everything
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// after __start non-code until the next label. So I add a label.
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start_hack:
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1: lw $gp, 0($ra)
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la $sp, kernel_stack + KERNEL_STACK_SIZE
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// Disable interrupts during bootstrap.
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mtc0 $zero, $Status
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// TODO: flush cache
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// Set kseg0 cachable.
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li $k0, 0x3
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mtc0 $k0, $Config, 0
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// Clear .bss
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la $a0, _edata
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la $a1, _end
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1: sw $zero, 0($a0)
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bne $a1, $a0, 1b
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addu $a0, 4
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// Set timer to a defined value
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mtc0 $zero, $Compare, 0
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// Use the interrupt vector for interrupts
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li $k0, 1 << 23
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mtc0 $k0, $Cause
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li $a0, 0xff0a0000
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la $t9, panic
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jr $t9
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// clear the tlb, hardwire page 0 to 0xffffffff
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// and soft-wire it to (0x294 << 20) + (0x290 << 10)
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// (for the idle task).
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// this address doesn't reach the tlb, so it can't trigger exceptions.
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mtc0 $zero, $PageMask
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mtc0 $zero, $EntryLo0
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mtc0 $zero, $EntryLo1
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li $t0, 0x80000000
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// There are 32 tlb entries.
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addi $a0, $zero, 31
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1: mtc0 $t0, $EntryHi
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mtc0 $a0, $Index
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tlbwi
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addiu $t0, $t0, 1 << 13
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bgtz $a0, 1b
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addiu $a0, $a0, -1
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la $t9, init
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jalr $t9
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nop
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sw $gp, -12($zero)
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save_args:
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sw $a0, 24($k0)
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sw $a1, 28($k0)
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sw $a2, 32($k0)
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sw $a3, 36($k0)
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sw $t1, 44($k0)
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sw $t2, 48($k0)
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sw $t3, 52($k0)
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sw $t4, 56($k0)
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sw $t5, 60($k0)
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sw $t6, 64($k0)
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sw $t7, 68($k0)
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sw $t8, 72($k0)
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sw $t9, 76($k0)
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sw $gp, 80($k0)
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j $ra
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run_idle:
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move $k0, $a0
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move $k1, $gp
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// Prepare enabling interrupts and switching to user mode.
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// The command is executed in the delay slot of the jump.
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li $t0, 0xff11
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// Now it's acceptable to receive an exception. Jump to kuseg,
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// thereby generating a tlb_refill exception (which is handled).
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// The address is the virtual address where the idle task is.
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la $t9, ((0x294 << 20) + (0x290 << 10) + 0x288)
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jr $t9
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mtc0 $t0, $Status
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kernel_exit:
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move $k0, $v0
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restore_regs
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eret
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