mirror of
git://projects.qi-hardware.com/iris.git
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229 lines
6.8 KiB
COBOL
229 lines
6.8 KiB
COBOL
#pypp 0
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// Iris: micro-kernel for a capability-based operating system.
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// mips/interrupts.ccp: Functions called by mips/entry.S.
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// Copyright 2009 Bas Wijnen <wijnen@debian.org>
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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#define ARCH
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#include "../kernel.hh"
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/// A TLB miss has occurred. This is the slow version. It is only used
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/// when k0 or k1 is not 0, or when an error occurs.
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/// Otherwise, the ultra-fast code in entry.S is used.
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Thread *tlb_refill ():
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//panic (0x88776655, "TLB refill")
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if !directory:
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panic (0x44449999, "No directory")
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unsigned EntryHi
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cp0_get (CP0_ENTRY_HI, EntryHi)
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unsigned *t = directory[EntryHi >> 21]
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if !t:
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (a)
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cp0_get (CP0_BAD_V_ADDR, a)
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dbg_send (a)
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panic (0x99992222, "No page table")
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// - 2 instead of - 1 means reset bit 0
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unsigned idx = (EntryHi >> 12) & ((1 << 9) - 2)
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cp0_set (CP0_ENTRY_LO0, t[idx])
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cp0_set (CP0_ENTRY_LO1, t[idx + 1])
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__asm__ volatile ("tlbwr")
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return current
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/// An interrupt which is not an exception has occurred.
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Thread *interrupt ():
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//panic (0x88877722, "Interrupt")
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//dbg_send (INTC_IPR)
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unsigned ipr = INTC_IPR
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for unsigned i = 0; i < 32; ++i:
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if ipr & (1 << i):
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// Handle timer interrupts specially: don't disable them.
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if i == IRQ_OST0:
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continue
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// Disable the interrupt while handling it.
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intc_mask_irq (i)
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intc_ack_irq (i)
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// Send message to interrupt handler.
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if arch_interrupt_receiver[i]:
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Capability::Context c
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for unsigned j = 0; j < 4; ++j:
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c.data[j] = 0
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c.cap[j] = NULL
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c.copy[j] = false
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arch_interrupt_receiver[i]->send_message (i, &c)
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if ipr & (1 << IRQ_OST0):
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ost_clear_uf (0)
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intc_ack_irq (IRQ_OST0)
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timer_interrupt ()
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return current
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void flush_tlb (unsigned asid):
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for unsigned tlb = 1; tlb < 32; ++tlb:
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cp0_set (CP0_INDEX, tlb)
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__asm__ volatile ("tlbr")
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unsigned hi
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cp0_get (CP0_ENTRY_HI, hi)
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if (hi & 0x1f) == asid:
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// Set asid to 0, which is only used by the idle task.
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cp0_set (CP0_ENTRY_HI, 0x2000 * tlb)
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__asm__ volatile ("tlbwi")
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static void arch_invoke ():
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Capability *target
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bool wait
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Thread *caller = current
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target = caller->address_space->find_capability (caller->arch.v0, &wait)
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if !target:
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// TODO: there must be no action here. This is just because the rest doesn't work yet.
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dbg_send (3, 2)
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//dbg_send (caller->arch.v0)
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schedule ()
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// Calling an invalid capability always fails.
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caller->arch.v0 = 0
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else:
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if wait:
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caller->wait ()
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Capability::Context c
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c.cap[0] = caller->address_space->find_capability (caller->arch.a0, &c.copy[0])
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c.cap[1] = caller->address_space->find_capability (caller->arch.a1, &c.copy[1])
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c.cap[2] = caller->address_space->find_capability (caller->arch.a2, &c.copy[2])
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c.cap[3] = caller->address_space->find_capability (caller->arch.a3, &c.copy[3])
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c.data[0] = caller->arch.t0
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c.data[1] = caller->arch.t1
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c.data[2] = caller->arch.t2
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c.data[3] = caller->arch.t3
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caller->arch.v0 = target->invoke (&c) ? 1 : 0
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if caller != current && caller != &idle && (caller->flags & (THREAD_FLAG_RUNNING | THREAD_FLAG_WAITING)) == THREAD_FLAG_RUNNING:
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current = caller
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else if !current:
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schedule ()
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if !current:
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current = &idle
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if caller != current:
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if (Memory *)asids[current->address_space->arch.asid] != current->address_space:
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if asids[0]:
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current->address_space->arch.asid = asids[0]
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asids[0] = asids[asids[0]]
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else:
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static unsigned random = 1
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current->address_space->arch.asid = random
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// Overwrite used asid, so flush those values from tlb.
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flush_tlb (random)
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++random
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if random >= 64:
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random = 1
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asids[current->address_space->arch.asid] = (unsigned)current->address_space
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cp0_set (CP0_ENTRY_HI, current->address_space->arch.asid)
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directory = current->address_space->arch.directory
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unsigned status
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cp0_get (CP0_STATUS, status)
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status &= 0x0fffffff
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if current->flags & THREAD_FLAG_PRIV:
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status |= 0x10000000
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cp0_set (CP0_STATUS, status | 0x13)
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/// A general exception has occurred.
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Thread *exception ():
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unsigned cause
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cp0_get (CP0_CAUSE, cause)
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switch (cause >> 2) & 0x1f:
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case 0:
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// Interrupt. This shouldn't happen, since CAUSE[IV] == 1.
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panic (0x11223344, "Interrupt on exception vector.")
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case 1:
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// TLB modification.
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panic (0x21223344, "TLB modification.")
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case 2:
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// TLB load or instruction fetch.
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (a)
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panic (0x31223344, "TLB load or instruction fetch.")
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case 3:
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// TLB store.
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panic (0x41223344, "TLB store.")
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case 4:
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// Address error load or instruction fetch.
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panic (0x51223344, "Address error load or instruction fetch.")
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case 5:
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// Address error store.
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unsigned a
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cp0_get (CP0_EPC, a)
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dbg_send (a, 16)
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panic (0x61223344, "Address error store.")
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case 6:
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// Bus error instruction fetch.
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panic (0x71223344, "Bus error instruction fetch.")
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case 7:
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// Bus error load or store.
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panic (0x81223344, "Bus error load or store.")
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case 8:
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// Syscall.
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current->pc += 4
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arch_invoke ()
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break
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case 9:
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// Breakpoint.
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panic (0x91223344, "Breakpoint.")
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case 10:
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// Reserved instruction.
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panic (0xa1223344, "Reserved instruction.")
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case 11:
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// Coprocessor unusable.
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panic (0xb1223344, "Coprocessor unusable.")
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case 12:
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// Arithmetic overflow.
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panic (0xc1223344, "Arithmetic overflow.")
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case 13:
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// Trap.
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panic (0xe1223344, "Trap.")
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case 15:
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// Floating point exception.
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panic (0xf1223344, "Floating point exception.")
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case 23:
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// Reference to WatchHi/WatchLo address.
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panic (0xf2223344, "Reference to WatchHi/WatchLo address.")
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case 24:
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// Machine check.
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panic (0xf3223344, "Machine check.")
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case 30:
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// Cache error (EJTAG only).
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panic (0xf4223344, "Cache error (EJTAG only).")
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case 14:
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 25:
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case 26:
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case 27:
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case 28:
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case 29:
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case 31:
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// Reserved.
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panic (0xf5223344, "Reserved exception code")
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default:
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panic (0xf6223344, "Impossible exception code")
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return current
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/// There's a cache error. Big trouble. Probably not worth trying to recover.
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Thread *cache_error ():
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panic (0x33333333, "cache error")
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return current
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