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components/lpc1100-qfn33.lib: remove dubious "R" (reserved) pin function

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NXP put "R" as the first name of some pins, e.g., R/PIO1_2/AD3/CT32B1_MAT
This is meant to indicate that it may have a possible extra function
which doesn't exist in the present implementation.

The whole concept seems bogus. First of all, there are several pins with
supposedly different roles but all with a common name. Second, one isn't
even supposed to set the pin configuration register to a value selecting
this "reserved" function. Third, there are several other pins that also
have unused codepoints in their function settings, e.g., PIO0_3 or
PIO0_4/SCL but there's no "R" in evidence there.

So that "R" doesnt seem to make any sense, may cause confusion, and
makes the symbol more crowded.
This commit is contained in:
Werner Almesberger 2012-12-20 19:45:19 -03:00
parent ecba9a3874
commit 1f0d15cc80
1 changed files with 5 additions and 5 deletions
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10
components/lpc1100-qfn33.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Thu Dec 20 18:25:48 2012 EESchema-LIBRARY Version 2.3 Date: Thu Dec 20 19:44:55 2012
#encoding utf-8 #encoding utf-8
# #
# LPC1100-QFN33 # LPC1100-QFN33
@ -21,16 +21,16 @@ X PIO0_4/SCL 10 -450 -1500 300 U 50 50 1 1 T
X PIO1_10/AD6/CT16B1_MAT1 20 2000 -150 300 L 50 50 1 1 T X PIO1_10/AD6/CT16B1_MAT1 20 2000 -150 300 L 50 50 1 1 T
X PIO1_5/nRTS/CT32B0_CAP0 30 -300 1600 300 D 50 50 1 1 T X PIO1_5/nRTS/CT32B0_CAP0 30 -300 1600 300 D 50 50 1 1 T
X PIO0_5/SDA 11 -300 -1500 300 U 50 50 1 1 T X PIO0_5/SDA 11 -300 -1500 300 U 50 50 1 1 T
X R/PIO0_11/AD0/CT32B0_MAT3 21 2000 0 300 L 50 50 1 1 T X PIO0_11/AD0/CT32B0_MAT3 21 2000 0 300 L 50 50 1 1 T
X PIO1_6/RXD/CT32B0_MAT0 31 -450 1600 300 D 50 50 1 1 T X PIO1_6/RXD/CT32B0_MAT0 31 -450 1600 300 D 50 50 1 1 T
X PIO1_9/CT16B1_MAT0 12 -150 -1500 300 U 50 50 1 1 T X PIO1_9/CT16B1_MAT0 12 -150 -1500 300 U 50 50 1 1 T
X R/PIO1_0/AD1/CT32B1_CAP0 22 2000 150 300 L 50 50 1 1 T X PIO1_0/AD1/CT32B1_CAP0 22 2000 150 300 L 50 50 1 1 T
X PIO1_7/TXD/CT32B0_MAT1 32 -600 1600 300 D 50 50 1 1 T X PIO1_7/TXD/CT32B0_MAT1 32 -600 1600 300 D 50 50 1 1 T
X PIO3_4 13 0 -1500 300 U 50 50 1 1 T X PIO3_4 13 0 -1500 300 U 50 50 1 1 T
X R/PIO1_1/AD2/CT32B1_MAT0 23 2000 300 300 L 50 50 1 1 T X PIO1_1/AD2/CT32B1_MAT0 23 2000 300 300 L 50 50 1 1 T
X VSS 33 900 -1500 300 U 50 50 1 1 W X VSS 33 900 -1500 300 U 50 50 1 1 W
X PIO3_5 14 150 -1500 300 U 50 50 1 1 T X PIO3_5 14 150 -1500 300 U 50 50 1 1 T
X R/PIO1_2/AD3/CT32B1_MAT1 24 2000 450 300 L 50 50 1 1 T X PIO1_2/AD3/CT32B1_MAT1 24 2000 450 300 L 50 50 1 1 T
X PIO0_6/SCK0 15 300 -1500 300 U 50 50 1 1 T X PIO0_6/SCK0 15 300 -1500 300 U 50 50 1 1 T
X SWDIO/PIO1_3/AD4/CT32B1_MAT2 25 450 1600 300 D 50 50 1 1 T X SWDIO/PIO1_3/AD4/CT32B1_MAT2 25 450 1600 300 D 50 50 1 1 T
X PIO0_7/nCTS 16 450 -1500 300 U 50 50 1 1 T X PIO0_7/nCTS 16 450 -1500 300 U 50 50 1 1 T