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modules/lga.fpd, HIERARCHY (LGA-12-1.7x2-RUT): TI "RUT" package
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@ -430,6 +430,7 @@ Quad
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LGA-16-3x3
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LGA-16-3x3
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LGA-8-2.5x2.5-BME280
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LGA-8-2.5x2.5-BME280
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LGA-20-3x4.5-BMX055
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LGA-20-3x4.5-BMX055
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LGA-12-1.7x2-RUT
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QFN
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QFN
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QFN16-LFCSP_LQ
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QFN16-LFCSP_LQ
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QFN20-UEEE
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QFN20-UEEE
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@ -72,12 +72,14 @@ frame pinsx {
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package "LGA-$pins-${sizex}x${sizey}${variant}"
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package "LGA-$pins-${sizex}x${sizey}${variant}"
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unit mm
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unit mm
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allow overlap
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table
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table
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{ variant, nx, ny, sx, sy, e, b, pxx, pxy, pyx, pyy, pe, cw }
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{ variant, nx, ny, sx, sy, e, b, pxx, pxy, pyx, pyy, pe, cw }
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{ "", 3, 5, 3mm, 3mm, 0.5mm, 0.1mm, 0.25mm, 0.35mm, pxx, pxy, 0.2mm, 0 }
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{ "", 3, 5, 3mm, 3mm, 0.5mm, 0.1mm, 0.25mm, 0.35mm, pxx, pxy, 0.2mm, 0 }
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{ "-BME280", 0, 4, 2.5mm, 2.5mm, 0.65mm, 0.125mm, 0.35mm, 0.35mm, pxx, pxy, 0.15mm, 1 }
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{ "-BME280", 0, 4, 2.5mm, 2.5mm, 0.65mm, 0.125mm, 0.35mm, 0.35mm, pxx, pxy, 0.15mm, 1 }
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{ "-BMX055", 3, 7, 3mm, 4.5mm, 0.5mm, 0.1mm, 0.25mm, 0.375mm, pxx, 0.475mm, 0.2mm, 1 }
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{ "-BMX055", 3, 7, 3mm, 4.5mm, 0.5mm, 0.1mm, 0.25mm, 0.375mm, pxx, 0.475mm, 0.2mm, 1 }
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{ "-RUT", 1, 5, 1.7mm, 2mm, 0.4mm, -0.1mm, 0.2mm, 0.6mm, pxx, pxy, 0mm, 0 }
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set pins = 2*(nx+ny)
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set pins = 2*(nx+ny)
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