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components/74x1g32_6.lib: single OR gate
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@ -46,6 +46,7 @@ Werner Almesberger <werner@almesberger.net>
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components/74x1g07_5.lib
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components/74x1g07_4.lib
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components/74x1g07_6.lib
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components/74x1g32_6.lib
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components/74x2g07_6.lib
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components/74x565.lib
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components/adxl32x.lib
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components/74x1g32_6.dcm
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components/74x1g32_6.dcm
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EESchema-DOCLIB Version 2.0
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#
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#End Doc Library
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components/74x1g32_6.lib
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components/74x1g32_6.lib
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# 74X1G32_6
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#
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DEF 74X1G32_6 U 0 40 Y N 1 F N
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F0 "U" -400 400 60 H V L CNN
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F1 "74X1G32_6" 50 -450 60 H V L CNN
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F2 "" 100 0 60 H I C CNN
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F3 "" 100 0 60 H I C CNN
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DRAW
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T 0 -300 150 50 0 0 0 A Normal 0 C C
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T 0 -300 -50 50 0 0 0 B Normal 0 C C
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T 0 0 -300 50 0 0 0 GND Normal 0 C C
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T 0 0 300 50 0 0 0 VCC Normal 0 C C
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T 0 300 50 50 0 0 0 Y Normal 0 C C
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A -400 0 250 0 369 0 1 0 N -150 0 -200 150
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A -400 0 250 0 -369 0 1 0 N -150 0 -200 -150
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A -159 -347 499 947 440 0 1 0 N -200 150 200 0
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A -158 347 499 -441 -948 0 1 0 N 200 0 -200 -150
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S -400 350 400 -350 0 1 0 N
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P 2 0 1 0 -400 -100 -175 -100 N
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P 2 0 1 0 -400 100 -175 100 N
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P 2 0 1 0 200 0 400 0 N
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X A 1 -600 100 200 R 50 50 1 1 I
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X B 2 -600 -100 200 R 50 50 1 1 I
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X GND 3 0 -550 200 U 50 50 1 1 W
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X Y 4 600 0 200 L 50 50 1 1 O
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X NC 5 600 -200 200 L 50 50 1 1 N
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X VCC 6 0 550 200 D 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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#End Library
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@ -21,6 +21,7 @@ Logic
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74x1g07_6
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74x1g08_5
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74x1g08_6
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74x1g32_6
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74x1g125
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Dual
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74x2g07_6
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@ -169,3 +169,4 @@ LibName97=./por
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LibName98=./tps6102x
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LibName99=./gencon
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LibName100=./74x2g07_6
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LibName101=./74x1g32_6
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