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changed FLG1/2 pins to output/Line.

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Adam Wang 2012-04-23 09:41:15 +08:00
parent e6d4981d39
commit be5f5bffd2
1 changed files with 3 additions and 3 deletions
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6
components/diodes_inc.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Fri 06 Apr 2012 15:26:06 CST
EESchema-LIBRARY Version 2.3 Date: Mon 23 Apr 2012 09:39:13 CST
#
# AP21X2A
#
@ -14,10 +14,10 @@ X GND 1 -600 -250 200 R 50 50 1 1 W
X IN 2 -600 250 200 R 50 50 1 1 I
X EN1 3 -600 50 200 R 50 50 1 1 I
X EN2 4 -600 -50 200 R 50 50 1 1 I
X FLG2 5 600 -250 200 L 50 50 1 1 E V
X FLG2 5 600 -250 200 L 50 50 1 1 O
X OUT2 6 600 -150 200 L 50 50 1 1 w
X OUT1 7 600 250 200 L 50 50 1 1 w
X FLG1 8 600 150 200 L 50 50 1 1 E V
X FLG1 8 600 150 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#